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Commit e9cf0f69 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.4.64 into android-4.4 



Changes in 4.4.64:
	KEYS: Disallow keyrings beginning with '.' to be joined as session keyrings
	KEYS: Change the name of the dead type to ".dead" to prevent user access
	KEYS: fix keyctl_set_reqkey_keyring() to not leak thread keyrings
	tracing: Allocate the snapshot buffer before enabling probe
	ring-buffer: Have ring_buffer_iter_empty() return true when empty
	cifs: Do not send echoes before Negotiate is complete
	CIFS: remove bad_network_name flag
	s390/mm: fix CMMA vs KSM vs others
	Drivers: hv: don't leak memory in vmbus_establish_gpadl()
	Drivers: hv: get rid of timeout in vmbus_open()
	Drivers: hv: vmbus: Reduce the delay between retries in vmbus_post_msg()
	VSOCK: Detach QP check should filter out non matching QPs.
	Input: elantech - add Fujitsu Lifebook E547 to force crc_enabled
	ACPI / power: Avoid maybe-uninitialized warning
	mmc: sdhci-esdhc-imx: increase the pad I/O drive strength for DDR50 card
	mac80211: reject ToDS broadcast data frames
	ubi/upd: Always flush after prepared for an update
	powerpc/kprobe: Fix oops when kprobed on 'stdu' instruction
	x86/mce/AMD: Give a name to MCA bank 3 when accessed with legacy MSRs
	kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd
	Tools: hv: kvp: ensure kvp device fd is closed on exec
	Drivers: hv: balloon: keep track of where ha_region starts
	Drivers: hv: balloon: account for gaps in hot add regions
	hv: don't reset hv_context.tsc_page on crash
	x86, pmem: fix broken __copy_user_nocache cache-bypass assumptions
	block: fix del_gendisk() vs blkdev_ioctl crash
	tipc: fix crash during node removal
	Linux 4.4.64

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents b878b260 12f4e1f5

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 4

PATCHLEVEL = 4

SUBLEVEL = 63

SUBLEVEL = 64

EXTRAVERSION =

NAME = Blurry Fish Butt

arch/arm/kvm/mmu.c

+12 −0
Original line number Diff line number Diff line
@@ -300,6 +300,14 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp, 
		next = kvm_pgd_addr_end(addr, end);

		if (!pgd_none(*pgd))

			unmap_puds(kvm, pgd, addr, next);

		/*

		 * If we are dealing with a large range in

		 * stage2 table, release the kvm->mmu_lock

		 * to prevent starvation and lockup detector

		 * warnings.

		 */

		if (kvm && (next != end))

			cond_resched_lock(&kvm->mmu_lock);

	} while (pgd++, addr = next, addr != end);

}
@@ -738,6 +746,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm) 
 */

static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)

{

	assert_spin_locked(&kvm->mmu_lock);

	unmap_range(kvm, kvm->arch.pgd, start, size);

}
@@ -824,7 +833,10 @@ void kvm_free_stage2_pgd(struct kvm *kvm) 
	if (kvm->arch.pgd == NULL)

		return;



	spin_lock(&kvm->mmu_lock);

	unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE);

	spin_unlock(&kvm->mmu_lock);



	kvm_free_hwpgd(kvm_get_hwpgd(kvm));

	if (KVM_PREALLOC_LEVEL > 0)

		kfree(kvm->arch.pgd);

arch/powerpc/kernel/entry_64.S

+3 −3
Original line number Diff line number Diff line
@@ -716,7 +716,7 @@ resume_kernel: 


	addi	r8,r1,INT_FRAME_SIZE	/* Get the kprobed function entry */



	lwz	r3,GPR1(r1)

	ld	r3,GPR1(r1)

	subi	r3,r3,INT_FRAME_SIZE	/* dst: Allocate a trampoline exception frame */

	mr	r4,r1			/* src:  current exception frame */

	mr	r1,r3			/* Reroute the trampoline frame to r1 */
@@ -730,8 +730,8 @@ resume_kernel: 
	addi	r6,r6,8

	bdnz	2b



	/* Do real store operation to complete stwu */

	lwz	r5,GPR1(r1)

	/* Do real store operation to complete stdu */

	ld	r5,GPR1(r1)

	std	r8,0(r5)



	/* Clear _TIF_EMULATE_STACK_STORE flag */

arch/s390/include/asm/pgtable.h

+2 −0
Original line number Diff line number Diff line
@@ -829,6 +829,8 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 
{

	pgste_t pgste;



	if (pte_present(entry))

		pte_val(entry) &= ~_PAGE_UNUSED;

	if (mm_has_pgste(mm)) {

		pgste = pgste_get_lock(ptep);

		pgste_val(pgste) &= ~_PGSTE_GPS_ZERO;

arch/x86/include/asm/pmem.h

+32 −13
Original line number Diff line number Diff line
@@ -72,8 +72,8 @@ static inline void arch_wmb_pmem(void) 
 * @size:	number of bytes to write back

 *

 * Write back a cache range using the CLWB (cache line write back)

 * instruction.  This function requires explicit ordering with an

 * arch_wmb_pmem() call.  This API is internal to the x86 PMEM implementation.

 * instruction. Note that @size is internally rounded up to be cache

 * line size aligned.

 */

static inline void __arch_wb_cache_pmem(void *vaddr, size_t size)

{
@@ -87,15 +87,6 @@ static inline void __arch_wb_cache_pmem(void *vaddr, size_t size) 
		clwb(p);

}



/*

 * copy_from_iter_nocache() on x86 only uses non-temporal stores for iovec

 * iterators, so for other types (bvec & kvec) we must do a cache write-back.

 */

static inline bool __iter_needs_pmem_wb(struct iov_iter *i)

{

	return iter_is_iovec(i) == false;

}



/**

 * arch_copy_from_iter_pmem - copy data from an iterator to PMEM

 * @addr:	PMEM destination address
@@ -114,8 +105,36 @@ static inline size_t arch_copy_from_iter_pmem(void __pmem *addr, size_t bytes, 
	/* TODO: skip the write-back by always using non-temporal stores */

	len = copy_from_iter_nocache(vaddr, bytes, i);



	if (__iter_needs_pmem_wb(i))

		__arch_wb_cache_pmem(vaddr, bytes);

	/*

	 * In the iovec case on x86_64 copy_from_iter_nocache() uses

	 * non-temporal stores for the bulk of the transfer, but we need

	 * to manually flush if the transfer is unaligned. A cached

	 * memory copy is used when destination or size is not naturally

	 * aligned. That is:

	 *   - Require 8-byte alignment when size is 8 bytes or larger.

	 *   - Require 4-byte alignment when size is 4 bytes.

	 *

	 * In the non-iovec case the entire destination needs to be

	 * flushed.

	 */

	if (iter_is_iovec(i)) {

		unsigned long flushed, dest = (unsigned long) addr;



		if (bytes < 8) {

			if (!IS_ALIGNED(dest, 4) || (bytes != 4))

				__arch_wb_cache_pmem(addr, 1);

		} else {

			if (!IS_ALIGNED(dest, 8)) {

				dest = ALIGN(dest, boot_cpu_data.x86_clflush_size);

				__arch_wb_cache_pmem(addr, 1);

			}



			flushed = dest - (unsigned long) addr;

			if (bytes > flushed && !IS_ALIGNED(bytes - flushed, 8))

				__arch_wb_cache_pmem(addr + bytes - 1, 1);

		}

	} else

		__arch_wb_cache_pmem(addr, bytes);



	return len;

}