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Commit e895e49b authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
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ARM: EXYNOS: Add support for MSHC controller clocks 



Add clock instances for bic("bus interface unit clock") and ciu("card
interface unit clock") of the all four MSHC controller instances.

Signed-off-by: default avatarAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent a0cabc40

arch/arm/mach-exynos/clock-exynos5.c

+16 −29
Original line number Diff line number Diff line
@@ -569,34 +569,29 @@ static struct clk exynos5_init_clocks_off[] = { 
		.enable		= exynos5_clk_ip_peris_ctrl,

		.ctrlbit	= (1 << 19),

	}, {

		.name		= "hsmmc",

		.devname	= "exynos4-sdhci.0",

		.name		= "biu",	/* bus interface unit clock */

		.devname	= "dw_mmc.0",

		.parent		= &exynos5_clk_aclk_200.clk,

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 12),

	}, {

		.name		= "hsmmc",

		.devname	= "exynos4-sdhci.1",

		.name		= "biu",

		.devname	= "dw_mmc.1",

		.parent		= &exynos5_clk_aclk_200.clk,

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 13),

	}, {

		.name		= "hsmmc",

		.devname	= "exynos4-sdhci.2",

		.name		= "biu",

		.devname	= "dw_mmc.2",

		.parent		= &exynos5_clk_aclk_200.clk,

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 14),

	}, {

		.name		= "hsmmc",

		.devname	= "exynos4-sdhci.3",

		.name		= "biu",

		.devname	= "dw_mmc.3",

		.parent		= &exynos5_clk_aclk_200.clk,

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 15),

	}, {

		.name		= "dwmci",

		.parent		= &exynos5_clk_aclk_200.clk,

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 16),

	}, {

		.name		= "sata",

		.devname	= "ahci",
@@ -1015,8 +1010,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = { 


static struct clksrc_clk exynos5_clk_sclk_mmc0 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "exynos4-sdhci.0",

		.name		= "ciu",	/* card interface unit clock */

		.devname	= "dw_mmc.0",

		.parent		= &exynos5_clk_dout_mmc0.clk,

		.enable		= exynos5_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 0),
@@ -1026,8 +1021,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = { 


static struct clksrc_clk exynos5_clk_sclk_mmc1 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "exynos4-sdhci.1",

		.name		= "ciu",

		.devname	= "dw_mmc.1",

		.parent		= &exynos5_clk_dout_mmc1.clk,

		.enable		= exynos5_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 4),
@@ -1037,8 +1032,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = { 


static struct clksrc_clk exynos5_clk_sclk_mmc2 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "exynos4-sdhci.2",

		.name		= "ciu",

		.devname	= "dw_mmc.2",

		.parent		= &exynos5_clk_dout_mmc2.clk,

		.enable		= exynos5_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 8),
@@ -1048,8 +1043,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = { 


static struct clksrc_clk exynos5_clk_sclk_mmc3 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "exynos4-sdhci.3",

		.name		= "ciu",

		.devname	= "dw_mmc.3",

		.parent		= &exynos5_clk_dout_mmc3.clk,

		.enable		= exynos5_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 12),
@@ -1122,14 +1117,6 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = { 


static struct clksrc_clk exynos5_clksrcs[] = {

	{

		.clk	= {

			.name		= "sclk_dwmci",

			.parent		= &exynos5_clk_dout_mmc4.clk,

			.enable		= exynos5_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 16),

		},

		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },

	}, {

		.clk	= {

			.name		= "sclk_fimd",

			.devname	= "s3cfb.1",