Merge "ARM: dts: msm: Update camera clock sources for sdm630" (e81f37a9) · Commits · e / devices / android_kernel_sony_msm8998

arch/arm/boot/dts/qcom/sdm630-camera.dtsi

+10 −10

Original line number	Diff line number	Diff line
		@@ -54,8 +54,8 @@
		"csiphy_timer_src_clk", "csiphy_timer_clk",
		"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
		"csiphy_ahb2crif";
		qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0
		0 384000000 0 0>;
		qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
		0 200000000 0 0>;
		status = "ok";
		};

		@@ -92,8 +92,8 @@
		"csiphy_timer_src_clk", "csiphy_timer_clk",
		"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
		"csiphy_ahb2crif";
		qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0
		0 384000000 0 0>;
		qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
		0 200000000 0 0>;
		status = "ok";
		};

		@@ -130,8 +130,8 @@
		"csiphy_timer_src_clk", "csiphy_timer_clk",
		"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
		"csiphy_ahb2crif";
		qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0
		0 384000000 0 0>;
		qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
		0 200000000 0 0>;
		status = "ok";
		};

		@@ -171,7 +171,7 @@
		"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
		"csi_clk", "csi_ahb_clk", "csi_rdi_clk",
		"csi_pix_clk", "cphy_csid_clk";
		qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000
		qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
		0 0 0 0 0>;
		status = "ok";
		};
		@@ -212,7 +212,7 @@
		"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
		"csi_clk", "csi_ahb_clk", "csi_rdi_clk",
		"csi_pix_clk", "cphy_csid_clk";
		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000
		qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
		0 0 0 0 0>;
		status = "ok";
		};
		@@ -253,7 +253,7 @@
		"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
		"csi_clk", "csi_ahb_clk", "csi_rdi_clk",
		"csi_pix_clk", "cphy_csid_clk";
		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000
		qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
		0 0 0 0 0>;
		status = "ok";
		};
		@@ -294,7 +294,7 @@
		"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
		"csi_clk", "csi_ahb_clk", "csi_rdi_clk",
		"csi_pix_clk", "cphy_csid_clk";
		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000
		qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
		0 0 0 0 0>;
		status = "ok";
		};