Loading drivers/clk/msm/clock-gcc-8998.c +0 −14 Original line number Diff line number Diff line Loading @@ -2207,18 +2207,6 @@ static struct branch_clk gcc_mss_cfg_ahb_clk = { }, }; static struct branch_clk gcc_mss_q6_bimc_axi_clk = { .cbcr_reg = GCC_MSS_Q6_BIMC_AXI_CBCR, .has_sibling = 1, .base = &virt_base, .c = { .dbg_name = "gcc_mss_q6_bimc_axi_clk", .always_on = true, .ops = &clk_ops_branch, CLK_INIT(gcc_mss_q6_bimc_axi_clk.c), }, }; static struct branch_clk gcc_mss_mnoc_bimc_axi_clk = { .cbcr_reg = GCC_MSS_MNOC_BIMC_AXI_CBCR, .has_sibling = 1, Loading Loading @@ -2406,7 +2394,6 @@ static struct mux_clk gcc_debug_mux = { { &gcc_dcc_ahb_clk.c, 0x0119 }, { &ipa_clk.c, 0x011b }, { &gcc_mss_cfg_ahb_clk.c, 0x011f }, { &gcc_mss_q6_bimc_axi_clk.c, 0x0124 }, { &gcc_mss_mnoc_bimc_axi_clk.c, 0x0120 }, { &gcc_mss_snoc_axi_clk.c, 0x0123 }, { &gcc_gpu_cfg_ahb_clk.c, 0x013b }, Loading Loading @@ -2646,7 +2633,6 @@ static struct clk_lookup msm_clocks_gcc_8998[] = { CLK_LIST(gcc_prng_ahb_clk), CLK_LIST(gcc_boot_rom_ahb_clk), CLK_LIST(gcc_mss_cfg_ahb_clk), CLK_LIST(gcc_mss_q6_bimc_axi_clk), CLK_LIST(gcc_mss_mnoc_bimc_axi_clk), CLK_LIST(gcc_mss_snoc_axi_clk), CLK_LIST(gcc_hdmi_clkref_clk), Loading include/dt-bindings/clock/msm-clocks-8998.h +0 −1 Original line number Diff line number Diff line Loading @@ -258,7 +258,6 @@ #define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 #define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f #define clk_gcc_mss_cfg_ahb_clk 0x111cde81 #define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 #define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f #define clk_gpll0_out_msscc 0x7d794829 #define clk_gcc_mss_snoc_axi_clk 0x0e71de85 Loading Loading
drivers/clk/msm/clock-gcc-8998.c +0 −14 Original line number Diff line number Diff line Loading @@ -2207,18 +2207,6 @@ static struct branch_clk gcc_mss_cfg_ahb_clk = { }, }; static struct branch_clk gcc_mss_q6_bimc_axi_clk = { .cbcr_reg = GCC_MSS_Q6_BIMC_AXI_CBCR, .has_sibling = 1, .base = &virt_base, .c = { .dbg_name = "gcc_mss_q6_bimc_axi_clk", .always_on = true, .ops = &clk_ops_branch, CLK_INIT(gcc_mss_q6_bimc_axi_clk.c), }, }; static struct branch_clk gcc_mss_mnoc_bimc_axi_clk = { .cbcr_reg = GCC_MSS_MNOC_BIMC_AXI_CBCR, .has_sibling = 1, Loading Loading @@ -2406,7 +2394,6 @@ static struct mux_clk gcc_debug_mux = { { &gcc_dcc_ahb_clk.c, 0x0119 }, { &ipa_clk.c, 0x011b }, { &gcc_mss_cfg_ahb_clk.c, 0x011f }, { &gcc_mss_q6_bimc_axi_clk.c, 0x0124 }, { &gcc_mss_mnoc_bimc_axi_clk.c, 0x0120 }, { &gcc_mss_snoc_axi_clk.c, 0x0123 }, { &gcc_gpu_cfg_ahb_clk.c, 0x013b }, Loading Loading @@ -2646,7 +2633,6 @@ static struct clk_lookup msm_clocks_gcc_8998[] = { CLK_LIST(gcc_prng_ahb_clk), CLK_LIST(gcc_boot_rom_ahb_clk), CLK_LIST(gcc_mss_cfg_ahb_clk), CLK_LIST(gcc_mss_q6_bimc_axi_clk), CLK_LIST(gcc_mss_mnoc_bimc_axi_clk), CLK_LIST(gcc_mss_snoc_axi_clk), CLK_LIST(gcc_hdmi_clkref_clk), Loading
include/dt-bindings/clock/msm-clocks-8998.h +0 −1 Original line number Diff line number Diff line Loading @@ -258,7 +258,6 @@ #define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 #define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f #define clk_gcc_mss_cfg_ahb_clk 0x111cde81 #define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 #define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f #define clk_gpll0_out_msscc 0x7d794829 #define clk_gcc_mss_snoc_axi_clk 0x0e71de85 Loading