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Commit e5776620 authored by Jacob Keller's avatar Jacob Keller Committed by Jeff Kirsher
Browse files

ixgbe: convert low_water into an array 



Since fc.high_water is an array, we should treat low_water as an array
also. This allows the algorithm to output different values for different
TCs, and then we can distinguish between them. In addition, this patch
changes one path that didn't honor the return value from ixgbe_setup_fc.

Reported-by: default avatarAaron Salter <aaron.k.salter@intel.com>
Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Tested-by: default avatarPhil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent fd0d192b

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

+16 −11
Original line number Diff line number Diff line
@@ -337,18 +337,24 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) 
	int i;

	bool link_up;



	/*

	 * Validate the water mark configuration for packet buffer 0.  Zero

	 * water marks indicate that the packet buffer was not configured

	 * and the watermarks for packet buffer 0 should always be configured.

	 */

	if (!hw->fc.low_water ||

	    !hw->fc.high_water[0] ||

	    !hw->fc.pause_time) {

	/* Validate the water mark configuration */

	if (!hw->fc.pause_time) {

		ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;

		goto out;

	}



	/* Low water mark of zero causes XOFF floods */

	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {

		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&

		    hw->fc.high_water[i]) {

			if (!hw->fc.low_water[i] ||

			    hw->fc.low_water[i] >= hw->fc.high_water[i]) {

				hw_dbg(hw, "Invalid water mark configuration\n");

				ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;

				goto out;

			}

		}

	}



	/*

	 * On 82598 having Rx FC on causes resets while doing 1G
@@ -432,12 +438,11 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) 
	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);

	IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);



	fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;



	/* Set up and enable Rx high/low water mark thresholds, enable XON. */

	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {

		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&

		    hw->fc.high_water[i]) {

			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;

			fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;

			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);

			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+22 −13
Original line number Diff line number Diff line
@@ -271,6 +271,7 @@ out: 
 **/

s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)

{

	s32 ret_val;

	u32 ctrl_ext;



	/* Set the media type */
@@ -292,12 +293,15 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 
	IXGBE_WRITE_FLUSH(hw);



	/* Setup flow control */

	ixgbe_setup_fc(hw);

	ret_val = ixgbe_setup_fc(hw);

	if (!ret_val)

		goto out;



	/* Clear adapter stopped flag */

	hw->adapter_stopped = false;



	return 0;

out:

	return ret_val;

}



/**
@@ -2106,18 +2110,24 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 
	u32 fcrtl, fcrth;

	int i;



	/*

	 * Validate the water mark configuration for packet buffer 0.  Zero

	 * water marks indicate that the packet buffer was not configured

	 * and the watermarks for packet buffer 0 should always be configured.

	 */

	if (!hw->fc.low_water ||

	    !hw->fc.high_water[0] ||

	    !hw->fc.pause_time) {

	/* Validate the water mark configuration. */

	if (!hw->fc.pause_time) {

		ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;

		goto out;

	}



	/* Low water mark of zero causes XOFF floods */

	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {

		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&

		    hw->fc.high_water[i]) {

			if (!hw->fc.low_water[i] ||

			    hw->fc.low_water[i] >= hw->fc.high_water[i]) {

				hw_dbg(hw, "Invalid water mark configuration\n");

				ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;

				goto out;

			}

		}

	}



	/* Negotiate the fc mode to use */

	ixgbe_fc_autoneg(hw);
@@ -2181,12 +2191,11 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 
	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);

	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);



	fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;



	/* Set up and enable Rx high/low water mark thresholds, enable XON. */

	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {

		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&

		    hw->fc.high_water[i]) {

			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;

			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);

			fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;

		} else {

drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c

+1 −1
Original line number Diff line number Diff line
@@ -208,7 +208,6 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) 


	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);



	fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;

	/* Configure PFC Tx thresholds per TC */

	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {

		if (!(pfc_en & (1 << i))) {
@@ -217,6 +216,7 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) 
			continue;

		}



		fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;

		reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;

		IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);

		IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);

drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c

+1 −1
Original line number Diff line number Diff line
@@ -242,7 +242,6 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) 
			max_tc = prio_tc[i];

	}



	fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;



	/* Configure PFC Tx thresholds per TC */

	for (i = 0; i <= max_tc; i++) {
@@ -257,6 +256,7 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) 


		if (enabled) {

			reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;

			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;

			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);

		} else {

			reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;

drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.h

+0 −2
Original line number Diff line number Diff line
@@ -81,9 +81,7 @@ struct ixgbe_fcoe { 
	void *extra_ddp_buffer;

	dma_addr_t extra_ddp_buffer_dma;

	unsigned long mode;

#ifdef CONFIG_IXGBE_DCB

	u8 up;

#endif

};



#endif /* _IXGBE_FCOE_H */