Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e37ddf27 authored by Alex Shi's avatar Alex Shi
Browse files

Merge tag 'v4.4.10' into linux-linaro-lsk-v4.4 

 This is the 4.4.10 stable release
parents 9ba733e2 4c2795dd

Documentation/devicetree/bindings/ata/ahci-platform.txt

+4 −0
Original line number Diff line number Diff line
@@ -30,6 +30,10 @@ Optional properties: 
- target-supply     : regulator for SATA target power

- phys              : reference to the SATA PHY node

- phy-names         : must be "sata-phy"

- ports-implemented : Mask that indicates which ports that the HBA supports

		      are available for software to use. Useful if PORTS_IMPL

		      is not programmed by the BIOS, which is true with

		      some embedded SOC's.



Required properties when using sub-nodes:

- #address-cells    : number of cells to encode an address

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -4097,8 +4097,8 @@ F: Documentation/efi-stub.txt 
F:	arch/ia64/kernel/efi.c

F:	arch/x86/boot/compressed/eboot.[ch]

F:	arch/x86/include/asm/efi.h

F:	arch/x86/platform/efi/*

F:	drivers/firmware/efi/*

F:	arch/x86/platform/efi/

F:	drivers/firmware/efi/

F:	include/linux/efi*.h



EFI VARIABLE FILESYSTEM

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 4

PATCHLEVEL = 4

SUBLEVEL = 9

SUBLEVEL = 10

EXTRAVERSION =

NAME = Blurry Fish Butt

arch/arc/include/asm/io.h

+18 −9
Original line number Diff line number Diff line
@@ -13,6 +13,15 @@ 
#include <asm/byteorder.h>

#include <asm/page.h>



#ifdef CONFIG_ISA_ARCV2

#include <asm/barrier.h>

#define __iormb()		rmb()

#define __iowmb()		wmb()

#else

#define __iormb()		do { } while (0)

#define __iowmb()		do { } while (0)

#endif



extern void __iomem *ioremap(unsigned long physaddr, unsigned long size);

extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,

				  unsigned long flags);
@@ -22,6 +31,15 @@ extern void iounmap(const void __iomem *addr); 
#define ioremap_wc(phy, sz)		ioremap(phy, sz)

#define ioremap_wt(phy, sz)		ioremap(phy, sz)



/*

 * io{read,write}{16,32}be() macros

 */

#define ioread16be(p)		({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })

#define ioread32be(p)		({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })



#define iowrite16be(v,p)	({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); })

#define iowrite32be(v,p)	({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); })



/* Change struct page to physical address */

#define page_to_phys(page)		(page_to_pfn(page) << PAGE_SHIFT)
@@ -99,15 +117,6 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr) 


}



#ifdef CONFIG_ISA_ARCV2

#include <asm/barrier.h>

#define __iormb()		rmb()

#define __iowmb()		wmb()

#else

#define __iormb()		do { } while (0)

#define __iowmb()		do { } while (0)

#endif



/*

 * MMIO can also get buffered/optimized in micro-arch, so barriers needed

 * Based on ARM model for the typical use case

arch/arm/mach-cns3xxx/pcie.c

+3 −3
Original line number Diff line number Diff line
@@ -220,13 +220,13 @@ static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci, 
	u32 mask = (0x1ull << (size * 8)) - 1;

	int shift = (where % 4) * 8;



	v = readl_relaxed(base + (where & 0xffc));

	v = readl_relaxed(base);



	v &= ~(mask << shift);

	v |= (val & mask) << shift;



	writel_relaxed(v, base + (where & 0xffc));

	readl_relaxed(base + (where & 0xffc));

	writel_relaxed(v, base);

	readl_relaxed(base);

}



static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)