Loading drivers/clk/msm/clock-gcc-8998.c +5 −44 Original line number Diff line number Diff line Loading @@ -239,28 +239,6 @@ static struct pll_vote_clk gpll4 = { }; DEFINE_EXT_CLK(gpll4_out_main, &gpll4.c); static struct clk_freq_tbl ftbl_hmss_ahb_clk_src[] = { F( 19200000, cxo_clk_src_ao, 1, 0, 0), F( 50000000, gpll0_out_main, 12, 0, 0), F( 100000000, gpll0_out_main, 6, 0, 0), F_END }; static struct rcg_clk hmss_ahb_clk_src = { .cmd_rcgr_reg = GCC_HMSS_AHB_CMD_RCGR, .set_rate = set_rate_hid, .freq_tbl = ftbl_hmss_ahb_clk_src, .current_freq = &rcg_dummy_freq, .base = &virt_base, .c = { .dbg_name = "hmss_ahb_clk_src", .ops = &clk_ops_rcg, VDD_DIG_FMAX_MAP3_AO(LOWER, 19200000, LOW, 50000000, NOMINAL, 100000000), CLK_INIT(hmss_ahb_clk_src.c), }, }; static struct clk_freq_tbl ftbl_usb30_master_clk_src[] = { F( 19200000, cxo_clk_src, 1, 0, 0), F( 60000000, gpll0_out_main, 10, 0, 0), Loading Loading @@ -1732,20 +1710,6 @@ static struct branch_clk gcc_gpu_iref_clk = { }, }; static struct local_vote_clk gcc_hmss_ahb_clk = { .cbcr_reg = GCC_HMSS_AHB_CBCR, .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, .en_mask = BIT(21), .base = &virt_base, .c = { .dbg_name = "gcc_hmss_ahb_clk", .always_on = true, .parent = &hmss_ahb_clk_src.c, .ops = &clk_ops_vote, CLK_INIT(gcc_hmss_ahb_clk.c), }, }; static struct branch_clk gcc_hmss_dvm_bus_clk = { .cbcr_reg = GCC_HMSS_DVM_BUS_CBCR, .has_sibling = 1, Loading Loading @@ -2408,7 +2372,6 @@ static struct mux_clk gcc_debug_mux = { { &gcc_ce1_ahb_m_clk.c, 0x0099 }, { &measure_only_bimc_hmss_axi_clk.c, 0x00bb }, { &gcc_bimc_gfx_clk.c, 0x00ac }, { &gcc_hmss_ahb_clk.c, 0x00ba }, { &gcc_hmss_rbcpr_clk.c, 0x00bc }, { &gcc_gp1_clk.c, 0x00df }, { &gcc_gp2_clk.c, 0x00e0 }, Loading Loading @@ -2531,7 +2494,6 @@ static struct clk_lookup msm_clocks_gcc_8998[] = { CLK_LIST(gcc_gpu_gpll0_div_clk), CLK_LIST(gpll4), CLK_LIST(gpll4_out_main), CLK_LIST(hmss_ahb_clk_src), CLK_LIST(usb30_master_clk_src), CLK_LIST(pcie_aux_clk_src), CLK_LIST(ufs_axi_clk_src), Loading Loading @@ -2629,7 +2591,6 @@ static struct clk_lookup msm_clocks_gcc_8998[] = { CLK_LIST(gcc_gpu_bimc_gfx_clk), CLK_LIST(gcc_gpu_cfg_ahb_clk), CLK_LIST(gcc_gpu_iref_clk), CLK_LIST(gcc_hmss_ahb_clk), CLK_LIST(gcc_hmss_dvm_bus_clk), CLK_LIST(gcc_hmss_rbcpr_clk), CLK_LIST(gcc_mmss_noc_cfg_ahb_clk), Loading Loading @@ -2742,12 +2703,12 @@ static int msm_gcc_8998_probe(struct platform_device *pdev) } /* * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be * turned off by hardware during certain apps low power modes. * Clear the HMSS_AHB_CLK_ENA bit to allow the gcc_hmss_ahb_clk clock * to be gated by RPM during VDD_MIN. */ regval = readl_relaxed(virt_base + GCC_APCS_CLOCK_SLEEP_ENA_VOTE); regval |= BIT(21); writel_relaxed(regval, virt_base + GCC_APCS_CLOCK_SLEEP_ENA_VOTE); regval = readl_relaxed(virt_base + GCC_APCS_CLOCK_BRANCH_ENA_VOTE); regval &= ~BIT(21); writel_relaxed(regval, virt_base + GCC_APCS_CLOCK_BRANCH_ENA_VOTE); vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); if (IS_ERR(vdd_dig.regulator[0])) { Loading include/dt-bindings/clock/msm-clocks-8998.h +1 −3 Original line number Diff line number Diff line /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -105,7 +105,6 @@ #define clk_gcc_gpu_gpll0_div_clk 0x07d16c6a #define clk_gpll4 0xb3b5d85b #define clk_gpll4_out_main 0xa9a0ab9d #define clk_hmss_ahb_clk_src 0xaec8450f #define clk_usb30_master_clk_src 0xc6262f89 #define clk_pcie_aux_clk_src 0xebc50566 #define clk_ufs_axi_clk_src 0x297ca380 Loading Loading @@ -201,7 +200,6 @@ #define clk_gcc_gpu_bimc_gfx_clk 0x3909459b #define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57 #define clk_gcc_gpu_iref_clk 0xfd82abad #define clk_gcc_hmss_ahb_clk 0x62818713 #define clk_gcc_hmss_dvm_bus_clk 0x17cc8b53 #define clk_gcc_hmss_rbcpr_clk 0x699183be #define clk_hmss_gpll0_clk_src 0x17eb05d0 Loading include/dt-bindings/clock/msm-clocks-hwio-8998.h +1 −3 Original line number Diff line number Diff line /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -66,7 +66,6 @@ #define CLOCK_FRQ_MEASURE_STATUS 0x62008 #define GCC_GPLL0_MODE 0x00000 #define GCC_GPLL4_MODE 0x77000 #define GCC_HMSS_AHB_CMD_RCGR 0x48014 #define GCC_USB30_MASTER_CMD_RCGR 0x0F014 #define GCC_PCIE_AUX_CMD_RCGR 0x6C000 #define GCC_UFS_AXI_CMD_RCGR 0x75018 Loading Loading @@ -169,7 +168,6 @@ #define GCC_GPU_BIMC_GFX_CBCR 0x71010 #define GCC_GPU_CFG_AHB_CBCR 0x71004 #define GCC_GPU_IREF_EN 0x88010 #define GCC_HMSS_AHB_CBCR 0x48000 #define GCC_HMSS_DVM_BUS_CBCR 0x4808C #define GCC_HMSS_RBCPR_CBCR 0x48008 #define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 Loading Loading
drivers/clk/msm/clock-gcc-8998.c +5 −44 Original line number Diff line number Diff line Loading @@ -239,28 +239,6 @@ static struct pll_vote_clk gpll4 = { }; DEFINE_EXT_CLK(gpll4_out_main, &gpll4.c); static struct clk_freq_tbl ftbl_hmss_ahb_clk_src[] = { F( 19200000, cxo_clk_src_ao, 1, 0, 0), F( 50000000, gpll0_out_main, 12, 0, 0), F( 100000000, gpll0_out_main, 6, 0, 0), F_END }; static struct rcg_clk hmss_ahb_clk_src = { .cmd_rcgr_reg = GCC_HMSS_AHB_CMD_RCGR, .set_rate = set_rate_hid, .freq_tbl = ftbl_hmss_ahb_clk_src, .current_freq = &rcg_dummy_freq, .base = &virt_base, .c = { .dbg_name = "hmss_ahb_clk_src", .ops = &clk_ops_rcg, VDD_DIG_FMAX_MAP3_AO(LOWER, 19200000, LOW, 50000000, NOMINAL, 100000000), CLK_INIT(hmss_ahb_clk_src.c), }, }; static struct clk_freq_tbl ftbl_usb30_master_clk_src[] = { F( 19200000, cxo_clk_src, 1, 0, 0), F( 60000000, gpll0_out_main, 10, 0, 0), Loading Loading @@ -1732,20 +1710,6 @@ static struct branch_clk gcc_gpu_iref_clk = { }, }; static struct local_vote_clk gcc_hmss_ahb_clk = { .cbcr_reg = GCC_HMSS_AHB_CBCR, .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, .en_mask = BIT(21), .base = &virt_base, .c = { .dbg_name = "gcc_hmss_ahb_clk", .always_on = true, .parent = &hmss_ahb_clk_src.c, .ops = &clk_ops_vote, CLK_INIT(gcc_hmss_ahb_clk.c), }, }; static struct branch_clk gcc_hmss_dvm_bus_clk = { .cbcr_reg = GCC_HMSS_DVM_BUS_CBCR, .has_sibling = 1, Loading Loading @@ -2408,7 +2372,6 @@ static struct mux_clk gcc_debug_mux = { { &gcc_ce1_ahb_m_clk.c, 0x0099 }, { &measure_only_bimc_hmss_axi_clk.c, 0x00bb }, { &gcc_bimc_gfx_clk.c, 0x00ac }, { &gcc_hmss_ahb_clk.c, 0x00ba }, { &gcc_hmss_rbcpr_clk.c, 0x00bc }, { &gcc_gp1_clk.c, 0x00df }, { &gcc_gp2_clk.c, 0x00e0 }, Loading Loading @@ -2531,7 +2494,6 @@ static struct clk_lookup msm_clocks_gcc_8998[] = { CLK_LIST(gcc_gpu_gpll0_div_clk), CLK_LIST(gpll4), CLK_LIST(gpll4_out_main), CLK_LIST(hmss_ahb_clk_src), CLK_LIST(usb30_master_clk_src), CLK_LIST(pcie_aux_clk_src), CLK_LIST(ufs_axi_clk_src), Loading Loading @@ -2629,7 +2591,6 @@ static struct clk_lookup msm_clocks_gcc_8998[] = { CLK_LIST(gcc_gpu_bimc_gfx_clk), CLK_LIST(gcc_gpu_cfg_ahb_clk), CLK_LIST(gcc_gpu_iref_clk), CLK_LIST(gcc_hmss_ahb_clk), CLK_LIST(gcc_hmss_dvm_bus_clk), CLK_LIST(gcc_hmss_rbcpr_clk), CLK_LIST(gcc_mmss_noc_cfg_ahb_clk), Loading Loading @@ -2742,12 +2703,12 @@ static int msm_gcc_8998_probe(struct platform_device *pdev) } /* * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be * turned off by hardware during certain apps low power modes. * Clear the HMSS_AHB_CLK_ENA bit to allow the gcc_hmss_ahb_clk clock * to be gated by RPM during VDD_MIN. */ regval = readl_relaxed(virt_base + GCC_APCS_CLOCK_SLEEP_ENA_VOTE); regval |= BIT(21); writel_relaxed(regval, virt_base + GCC_APCS_CLOCK_SLEEP_ENA_VOTE); regval = readl_relaxed(virt_base + GCC_APCS_CLOCK_BRANCH_ENA_VOTE); regval &= ~BIT(21); writel_relaxed(regval, virt_base + GCC_APCS_CLOCK_BRANCH_ENA_VOTE); vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); if (IS_ERR(vdd_dig.regulator[0])) { Loading
include/dt-bindings/clock/msm-clocks-8998.h +1 −3 Original line number Diff line number Diff line /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -105,7 +105,6 @@ #define clk_gcc_gpu_gpll0_div_clk 0x07d16c6a #define clk_gpll4 0xb3b5d85b #define clk_gpll4_out_main 0xa9a0ab9d #define clk_hmss_ahb_clk_src 0xaec8450f #define clk_usb30_master_clk_src 0xc6262f89 #define clk_pcie_aux_clk_src 0xebc50566 #define clk_ufs_axi_clk_src 0x297ca380 Loading Loading @@ -201,7 +200,6 @@ #define clk_gcc_gpu_bimc_gfx_clk 0x3909459b #define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57 #define clk_gcc_gpu_iref_clk 0xfd82abad #define clk_gcc_hmss_ahb_clk 0x62818713 #define clk_gcc_hmss_dvm_bus_clk 0x17cc8b53 #define clk_gcc_hmss_rbcpr_clk 0x699183be #define clk_hmss_gpll0_clk_src 0x17eb05d0 Loading
include/dt-bindings/clock/msm-clocks-hwio-8998.h +1 −3 Original line number Diff line number Diff line /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -66,7 +66,6 @@ #define CLOCK_FRQ_MEASURE_STATUS 0x62008 #define GCC_GPLL0_MODE 0x00000 #define GCC_GPLL4_MODE 0x77000 #define GCC_HMSS_AHB_CMD_RCGR 0x48014 #define GCC_USB30_MASTER_CMD_RCGR 0x0F014 #define GCC_PCIE_AUX_CMD_RCGR 0x6C000 #define GCC_UFS_AXI_CMD_RCGR 0x75018 Loading Loading @@ -169,7 +168,6 @@ #define GCC_GPU_BIMC_GFX_CBCR 0x71010 #define GCC_GPU_CFG_AHB_CBCR 0x71004 #define GCC_GPU_IREF_EN 0x88010 #define GCC_HMSS_AHB_CBCR 0x48000 #define GCC_HMSS_DVM_BUS_CBCR 0x4808C #define GCC_HMSS_RBCPR_CBCR 0x48008 #define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 Loading