Loading Documentation/devicetree/bindings/net/wireless/qcom,wcn3990-wifi.txt 0 → 100644 +16 −0 Original line number Diff line number Diff line * Qualcomm Technologies, Inc. WCN3990 chipset WLAN platform Driver This driver adds support for the Integrated WCN3990 WLAN module, WCN3990 is integrated 802.11ac chipset with SNOC bus interface. It also add support for SNOC bus registration, copy engine configuration for the WCN3990 chipset, shadow register configuration, create host to target communication interface to interact with WLAN firmware, WLAN module interface control and data receive(RX)/transmit(TX) control. Required properties: - compatible: "qcom,wcn3990-wifi"; Example: qcom,msm_ath10k@18000000 { compatible = "qcom,wcn3990-wifi"; }; drivers/net/wireless/ath/ath10k/htc.c +8 −0 Original line number Diff line number Diff line Loading @@ -451,8 +451,16 @@ static const char *htc_service_name(enum ath10k_htc_svc_id id) return "NMI Data"; case ATH10K_HTC_SVC_ID_HTT_DATA_MSG: return "HTT Data"; case ATH10K_HTC_SVC_ID_HTT_DATA2_MSG: return "HTT Data"; case ATH10K_HTC_SVC_ID_HTT_DATA3_MSG: return "HTT Data"; case ATH10K_HTC_SVC_ID_HTT_IPA_MSG: return "IPA"; case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS: return "RAW"; case ATH10K_HTC_SVC_ID_HTT_LOG_MSG: return "PKTLOG"; } return "Unknown"; Loading drivers/net/wireless/ath/ath10k/htc.h +6 −2 Original line number Diff line number Diff line Loading @@ -222,7 +222,8 @@ enum ath10k_htc_svc_gid { ATH10K_HTC_SVC_GRP_WMI = 1, ATH10K_HTC_SVC_GRP_NMI = 2, ATH10K_HTC_SVC_GRP_HTT = 3, ATH10K_IPA_SERVICE_GROUP = 5, ATH10K_LOG_SERVICE_GROUP = 6, ATH10K_HTC_SVC_GRP_TEST = 254, ATH10K_HTC_SVC_GRP_LAST = 255, }; Loading @@ -246,7 +247,10 @@ enum ath10k_htc_svc_id { ATH10K_HTC_SVC_ID_NMI_DATA = SVC(ATH10K_HTC_SVC_GRP_NMI, 1), ATH10K_HTC_SVC_ID_HTT_DATA_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 0), ATH10K_HTC_SVC_ID_HTT_DATA2_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 1), ATH10K_HTC_SVC_ID_HTT_DATA3_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 2), ATH10K_HTC_SVC_ID_HTT_IPA_MSG = SVC(ATH10K_IPA_SERVICE_GROUP, 0), ATH10K_HTC_SVC_ID_HTT_LOG_MSG = SVC(ATH10K_LOG_SERVICE_GROUP, 0), /* raw stream service (i.e. flash, tcmd, calibration apps) */ ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS = SVC(ATH10K_HTC_SVC_GRP_TEST, 0), }; Loading drivers/net/wireless/ath/ath10k/snoc.c 0 → 100644 +704 −0 Original line number Diff line number Diff line /* Copyright (c) 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <linux/module.h> #include <linux/kernel.h> #include "debug.h" #include "hif.h" #include "htc.h" #include "ce.h" #include "snoc.h" #include <soc/qcom/icnss.h> #include <linux/of.h> #include <linux/platform_device.h> static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); static struct ce_attr host_ce_config_wlan[] = { /* CE0: host->target HTC control streams */ { .flags = CE_ATTR_FLAGS, .src_nentries = 16, .src_sz_max = 2048, .dest_nentries = 0, .send_cb = ath10k_snoc_htc_tx_cb, }, /* CE1: target->host HTT + HTC control */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 512, .recv_cb = ath10k_snoc_htt_htc_rx_cb, }, /* CE2: target->host WMI */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 64, .recv_cb = ath10k_snoc_htc_rx_cb, }, /* CE3: host->target WMI */ { .flags = CE_ATTR_FLAGS, .src_nentries = 32, .src_sz_max = 2048, .dest_nentries = 0, .send_cb = ath10k_snoc_htc_tx_cb, }, /* CE4: host->target HTT */ { .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, .src_nentries = 256, .src_sz_max = 256, .dest_nentries = 0, .send_cb = ath10k_snoc_htt_tx_cb, }, /* CE5: target->host HTT (ipa_uc->target ) */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 512, .dest_nentries = 512, .recv_cb = ath10k_snoc_htt_rx_cb, }, /* CE6: target autonomous hif_memcpy */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 0, .dest_nentries = 0, }, /* CE7: ce_diag, the Diagnostic Window */ { .flags = CE_ATTR_FLAGS, .src_nentries = 2, .src_sz_max = 2048, .dest_nentries = 2, }, /* CE8: Target to uMC */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 128, }, /* CE9 target->host HTT */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 512, .recv_cb = ath10k_snoc_htt_htc_rx_cb, }, /* CE10: target->host HTT */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 512, .recv_cb = ath10k_snoc_htt_htc_rx_cb, }, /* CE11: target -> host PKTLOG */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 512, .recv_cb = ath10k_snoc_htt_htc_rx_cb, }, }; static struct ce_pipe_config target_ce_config_wlan[] = { /* CE0: host->target HTC control and raw streams */ { .pipenum = __cpu_to_le32(0), .pipedir = __cpu_to_le32(PIPEDIR_OUT), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE1: target->host HTT + HTC control */ { .pipenum = __cpu_to_le32(1), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE2: target->host WMI */ { .pipenum = __cpu_to_le32(2), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(64), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE3: host->target WMI */ { .pipenum = __cpu_to_le32(3), .pipedir = __cpu_to_le32(PIPEDIR_OUT), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE4: host->target HTT */ { .pipenum = __cpu_to_le32(4), .pipedir = __cpu_to_le32(PIPEDIR_OUT), .nentries = __cpu_to_le32(256), .nbytes_max = __cpu_to_le32(256), .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), .reserved = __cpu_to_le32(0), }, /* CE5: target->host HTT (HIF->HTT) */ { .pipenum = __cpu_to_le32(5), .pipedir = __cpu_to_le32(PIPEDIR_OUT), .nentries = __cpu_to_le32(1024), .nbytes_max = __cpu_to_le32(64), .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), .reserved = __cpu_to_le32(0), }, /* CE6: Reserved for target autonomous hif_memcpy */ { .pipenum = __cpu_to_le32(6), .pipedir = __cpu_to_le32(PIPEDIR_INOUT), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(16384), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE7 used only by Host */ { .pipenum = __cpu_to_le32(7), .pipedir = __cpu_to_le32(4), .nentries = __cpu_to_le32(0), .nbytes_max = __cpu_to_le32(0), .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), .reserved = __cpu_to_le32(0), }, /* CE8 Target to uMC */ { .pipenum = __cpu_to_le32(8), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(0), .reserved = __cpu_to_le32(0), }, /* CE9 target->host HTT */ { .pipenum = __cpu_to_le32(9), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE10 target->host HTT */ { .pipenum = __cpu_to_le32(10), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE11 target autonomous qcache memcpy */ { .pipenum = __cpu_to_le32(11), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, }; static struct service_to_pipe target_service_to_ce_map_wlan[] = { { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(0), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { /* not used */ __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(0), }, { /* not used */ __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(4), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(1), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_IPA_MSG), __cpu_to_le32(PIPEDIR_OUT),/* IPA service */ __cpu_to_le32(5), }, { /* in = DL = target -> host */ __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(9), }, { /* in = DL = target -> host */ __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(10), }, { /* in = DL = target -> host pktlog */ __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(11), }, /* (Additions here) */ { /* must be last */ __cpu_to_le32(0), __cpu_to_le32(0), __cpu_to_le32(0), }, }; void ath10k_snoc_write32(void *ar, u32 offset, u32 value) { } u32 ath10k_snoc_read32(void *ar, u32 offset) { u32 val = 0; return val; } static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe *pipe) { struct ath10k *ar = pipe->hif_ce_state; struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; struct sk_buff *skb; dma_addr_t paddr; int ret; skb = dev_alloc_skb(pipe->buf_sz); if (!skb) return -ENOMEM; WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); paddr = dma_map_single(ar->dev, skb->data, skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); if (unlikely(dma_mapping_error(ar->dev, paddr))) { ath10k_warn(ar, "failed to dma map snoc rx buf\n"); dev_kfree_skb_any(skb); return -EIO; } ATH10K_SKB_RXCB(skb)->paddr = paddr; spin_lock_bh(&ar_snoc->ce_lock); ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr); spin_unlock_bh(&ar_snoc->ce_lock); if (ret) { dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); dev_kfree_skb_any(skb); return ret; } return 0; } static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe *pipe) { struct ath10k *ar = pipe->hif_ce_state; struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; int ret, num; if (pipe->buf_sz == 0) return; if (!ce_pipe->dest_ring) return; spin_lock_bh(&ar_snoc->ce_lock); num = __ath10k_ce_rx_num_free_bufs(ce_pipe); spin_unlock_bh(&ar_snoc->ce_lock); while (num--) { ret = __ath10k_snoc_rx_post_buf(pipe); if (ret) { if (ret == -ENOSPC) break; ath10k_warn(ar, "failed to post rx buf: %d\n", ret); mod_timer(&ar_snoc->rx_post_retry, jiffies + ATH10K_SNOC_RX_POST_RETRY_MS); break; } } } static void ath10k_snoc_rx_post(struct ath10k *ar) { struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); int i; for (i = 0; i < CE_COUNT; i++) ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]); } static void ath10k_snoc_rx_replenish_retry(unsigned long ptr) { struct ath10k *ar = (void *)ptr; ath10k_snoc_rx_post(ar); } static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state) { struct ath10k *ar = ce_state->ar; struct sk_buff_head list; struct sk_buff *skb; __skb_queue_head_init(&list); while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { if (!skb) continue; __skb_queue_tail(&list, skb); } while ((skb = __skb_dequeue(&list))) ath10k_htc_tx_completion_handler(ar, skb); } static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe *ce_state, void (*callback)(struct ath10k *ar, struct sk_buff *skb)) { struct ath10k *ar = ce_state->ar; struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); struct ath10k_snoc_pipe *pipe_info = &ar_snoc->pipe_info[ce_state->id]; struct sk_buff *skb; struct sk_buff_head list; void *transfer_context; unsigned int nbytes, max_nbytes; __skb_queue_head_init(&list); while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, &nbytes) == 0) { skb = transfer_context; max_nbytes = skb->len + skb_tailroom(skb); dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, max_nbytes, DMA_FROM_DEVICE); if (unlikely(max_nbytes < nbytes)) { ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", nbytes, max_nbytes); dev_kfree_skb_any(skb); continue; } skb_put(skb, nbytes); __skb_queue_tail(&list, skb); } while ((skb = __skb_dequeue(&list))) { ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc rx ce pipe %d len %d\n", ce_state->id, skb->len); callback(ar, skb); } ath10k_snoc_rx_post_pipe(pipe_info); } static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state) { ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); } static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) { /* CE4 polling needs to be done whenever CE pipe which transports * HTT Rx (target->host) is processed. */ ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE); ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); } static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state) { struct ath10k *ar = ce_state->ar; struct sk_buff *skb; while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { /* no need to call tx completion for NULL pointers */ if (!skb) continue; dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, skb->len, DMA_TO_DEVICE); ath10k_htt_hif_tx_complete(ar, skb); } } static void ath10k_snoc_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) { skb_pull(skb, sizeof(struct ath10k_htc_hdr)); ath10k_htt_t2h_msg_handler(ar, skb); } static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state) { /* CE4 polling needs to be done whenever CE pipe which transports * HTT Rx (target->host) is processed. */ ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE); ath10k_snoc_process_rx_cb(ce_state, ath10k_snoc_htt_rx_deliver); } static int ath10k_snoc_hif_tx_sg(struct ath10k *ar, u8 pipe_id, struct ath10k_hif_sg_item *items, int n_items) { return 0; } static u16 ath10k_snoc_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) { return 0; } static void ath10k_snoc_hif_send_complete_check(struct ath10k *ar, u8 pipe, int force) { } static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, u8 *ul_pipe, u8 *dl_pipe) { return 0; } static void ath10k_snoc_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe, u8 *dl_pipe) { } static void ath10k_snoc_hif_stop(struct ath10k *ar) { } static void ath10k_snoc_hif_power_down(struct ath10k *ar) { } static int ath10k_snoc_hif_start(struct ath10k *ar) { return 0; } static int ath10k_snoc_hif_power_up(struct ath10k *ar) { return 0; } static const struct ath10k_hif_ops ath10k_snoc_hif_ops = { .tx_sg = ath10k_snoc_hif_tx_sg, .start = ath10k_snoc_hif_start, .stop = ath10k_snoc_hif_stop, .map_service_to_pipe = ath10k_snoc_hif_map_service_to_pipe, .get_default_pipe = ath10k_snoc_hif_get_default_pipe, .send_complete_check = ath10k_snoc_hif_send_complete_check, .get_free_queue_number = ath10k_snoc_hif_get_free_queue_number, .power_up = ath10k_snoc_hif_power_up, .power_down = ath10k_snoc_hif_power_down, .read32 = ath10k_snoc_read32, .write32 = ath10k_snoc_write32, }; static int ath10k_snoc_probe(struct platform_device *pdev) { int ret = 0; struct ath10k *ar; struct ath10k_snoc *ar_snoc; enum ath10k_hw_rev hw_rev; struct device *dev; dev = &pdev->dev; hw_rev = ATH10K_HW_WCN3990; ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(37)); ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC, hw_rev, &ath10k_snoc_hif_ops); if (!ar) { dev_err(dev, "failed to allocate core\n"); return -ENOMEM; } ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 probed\n", __func__); return ret; } static int ath10k_snoc_remove(struct platform_device *pdev) { struct ath10k *ar = platform_get_drvdata(pdev); struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); if (!ar) return -EINVAL; if (!ar_snoc) return -EINVAL; ath10k_core_destroy(ar); ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 removed\n", __func__); return 0; } static const struct of_device_id ath10k_snoc_dt_match[] = { {.compatible = "qcom,wcn3990-wifi"}, {} }; MODULE_DEVICE_TABLE(of, ath10k_snoc_dt_match); static struct platform_driver ath10k_snoc_driver = { .probe = ath10k_snoc_probe, .remove = ath10k_snoc_remove, .driver = { .name = "ath10k_snoc", .owner = THIS_MODULE, .of_match_table = ath10k_snoc_dt_match, }, }; static int __init ath10k_snoc_init(void) { int ret; ret = platform_driver_register(&ath10k_snoc_driver); if (ret) pr_err("failed to register ath10k snoc driver: %d\n", ret); return ret; } module_init(ath10k_snoc_init); static void __exit ath10k_snoc_exit(void) { platform_driver_unregister(&ath10k_snoc_driver); } module_exit(ath10k_snoc_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices"); drivers/net/wireless/ath/ath10k/snoc.h 0 → 100644 +204 −0 Original line number Diff line number Diff line /* Copyright (c) 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef _SNOC_H_ #define _SNOC_H_ #include "hw.h" #include "ce.h" #include "pci.h" #define ATH10K_SNOC_RX_POST_RETRY_MS 50 #define CE_POLL_PIPE 4 /* struct snoc_state: SNOC target state * @pipe_cfg_addr: pipe configuration address * @svc_to_pipe_map: pipe services */ struct snoc_state { u32 pipe_cfg_addr; u32 svc_to_pipe_map; }; /* struct ath10k_snoc_pipe: SNOC pipe configuration * @ath10k_ce_pipe: pipe handle * @pipe_num: pipe number * @hif_ce_state: pointer to ce state * @buf_sz: buffer size * @pipe_lock: pipe lock * @ar_snoc: snoc private structure * @intr: tasklet structure */ struct ath10k_snoc_pipe { struct ath10k_ce_pipe *ce_hdl; u8 pipe_num; struct ath10k *hif_ce_state; size_t buf_sz; /* protect ce info */ spinlock_t pipe_lock; struct ath10k_snoc *ar_snoc; struct tasklet_struct intr; }; /* struct ath10k_snoc_supp_chip: supported chip set * @dev_id: device id * @rev_id: revison id */ struct ath10k_snoc_supp_chip { u32 dev_id; u32 rev_id; }; /* struct ath10k_snoc_info: SNOC info struct * @v_addr: base virtual address * @p_addr: base physical address * @chip_id: chip id * @chip_family: chip family * @board_id: board id * @soc_id: soc id * @fw_version: fw version */ struct ath10k_snoc_info { void __iomem *v_addr; phys_addr_t p_addr; u32 chip_id; u32 chip_family; u32 board_id; u32 soc_id; u32 fw_version; }; /* struct ath10k_target_info: SNOC target info * @target_version: target version * @target_type: target type * @target_revision: target revision * @soc_version: target soc version */ struct ath10k_target_info { u32 target_version; u32 target_type; u32 target_revision; u32 soc_version; }; /* struct ath10k_snoc: SNOC info struct * @dev: device structure * @ar:ath10k base structure * @mem: mem base virtual address * @mem_pa: mem base physical address * @target_info: snoc target info * @mem_len: mempry map length * @intr_tq: rx tasklet handle * @pipe_info: pipe info struct * @ce_lock: protect ce structures * @ce_states: maps ce id to ce state * @rx_post_retry: rx buffer post processing timer * @vaddr_rri_on_ddr: virtual address for RRI * @is_driver_probed: flag to indicate driver state */ struct ath10k_snoc { struct device *dev; struct ath10k *ar; void __iomem *mem; dma_addr_t mem_pa; struct ath10k_target_info target_info; size_t mem_len; struct tasklet_struct intr_tq; struct ath10k_snoc_pipe pipe_info[CE_COUNT_MAX]; /* protects CE info */ spinlock_t ce_lock; struct ath10k_ce_pipe ce_states[CE_COUNT_MAX]; struct timer_list rx_post_retry; u32 *vaddr_rri_on_ddr; bool is_driver_probed; }; /* struct ath10k_ce_tgt_pipe_cfg: target pipe configuration * @pipe_num: pipe number * @pipe_dir: pipe direction * @nentries: entries in pipe * @nbytes_max: pipe max size * @flags: pipe flags * @reserved: reserved */ struct ath10k_ce_tgt_pipe_cfg { u32 pipe_num; u32 pipe_dir; u32 nentries; u32 nbytes_max; u32 flags; u32 reserved; }; /* struct ath10k_ce_svc_pipe_cfg: service pipe configuration * @service_id: target version * @pipe_dir: pipe direction * @pipe_num: pipe number */ struct ath10k_ce_svc_pipe_cfg { u32 service_id; u32 pipe_dir; u32 pipe_num; }; /* struct ath10k_shadow_reg_cfg: shadow register configuration * @ce_id: copy engine id * @reg_offset: offset to copy engine */ struct ath10k_shadow_reg_cfg { u16 ce_id; u16 reg_offset; }; /* struct ath10k_wlan_enable_cfg: wlan enable configuration * @num_ce_tgt_cfg: no of ce target configuration * @ce_tgt_cfg: target ce configuration * @num_ce_svc_pipe_cfg: no of ce service configuration * @ce_svc_cfg: ce service configuration * @num_shadow_reg_cfg: no of shadow registers * @shadow_reg_cfg: shadow register configuration */ struct ath10k_wlan_enable_cfg { u32 num_ce_tgt_cfg; struct ath10k_ce_tgt_pipe_cfg *ce_tgt_cfg; u32 num_ce_svc_pipe_cfg; struct ath10k_ce_svc_pipe_cfg *ce_svc_cfg; u32 num_shadow_reg_cfg; struct ath10k_shadow_reg_cfg *shadow_reg_cfg; }; /* enum ath10k_driver_mode: ath10k driver mode * @ATH10K_MISSION: mission mode * @ATH10K_FTM: ftm mode * @ATH10K_EPPING: epping mode * @ATH10K_OFF: off mode */ enum ath10k_driver_mode { ATH10K_MISSION, ATH10K_FTM, ATH10K_EPPING, ATH10K_OFF }; static inline struct ath10k_snoc *ath10k_snoc_priv(struct ath10k *ar) { return (struct ath10k_snoc *)ar->drv_priv; } void ath10k_snoc_write32(void *ar, u32 offset, u32 value); void ath10k_snoc_soc_write32(struct ath10k *ar, u32 addr, u32 val); void ath10k_snoc_reg_write32(struct ath10k *ar, u32 addr, u32 val); u32 ath10k_snoc_read32(void *ar, u32 offset); u32 ath10k_snoc_soc_read32(struct ath10k *ar, u32 addr); u32 ath10k_snoc_reg_read32(struct ath10k *ar, u32 addr); #endif /* _SNOC_H_ */ Loading
Documentation/devicetree/bindings/net/wireless/qcom,wcn3990-wifi.txt 0 → 100644 +16 −0 Original line number Diff line number Diff line * Qualcomm Technologies, Inc. WCN3990 chipset WLAN platform Driver This driver adds support for the Integrated WCN3990 WLAN module, WCN3990 is integrated 802.11ac chipset with SNOC bus interface. It also add support for SNOC bus registration, copy engine configuration for the WCN3990 chipset, shadow register configuration, create host to target communication interface to interact with WLAN firmware, WLAN module interface control and data receive(RX)/transmit(TX) control. Required properties: - compatible: "qcom,wcn3990-wifi"; Example: qcom,msm_ath10k@18000000 { compatible = "qcom,wcn3990-wifi"; };
drivers/net/wireless/ath/ath10k/htc.c +8 −0 Original line number Diff line number Diff line Loading @@ -451,8 +451,16 @@ static const char *htc_service_name(enum ath10k_htc_svc_id id) return "NMI Data"; case ATH10K_HTC_SVC_ID_HTT_DATA_MSG: return "HTT Data"; case ATH10K_HTC_SVC_ID_HTT_DATA2_MSG: return "HTT Data"; case ATH10K_HTC_SVC_ID_HTT_DATA3_MSG: return "HTT Data"; case ATH10K_HTC_SVC_ID_HTT_IPA_MSG: return "IPA"; case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS: return "RAW"; case ATH10K_HTC_SVC_ID_HTT_LOG_MSG: return "PKTLOG"; } return "Unknown"; Loading
drivers/net/wireless/ath/ath10k/htc.h +6 −2 Original line number Diff line number Diff line Loading @@ -222,7 +222,8 @@ enum ath10k_htc_svc_gid { ATH10K_HTC_SVC_GRP_WMI = 1, ATH10K_HTC_SVC_GRP_NMI = 2, ATH10K_HTC_SVC_GRP_HTT = 3, ATH10K_IPA_SERVICE_GROUP = 5, ATH10K_LOG_SERVICE_GROUP = 6, ATH10K_HTC_SVC_GRP_TEST = 254, ATH10K_HTC_SVC_GRP_LAST = 255, }; Loading @@ -246,7 +247,10 @@ enum ath10k_htc_svc_id { ATH10K_HTC_SVC_ID_NMI_DATA = SVC(ATH10K_HTC_SVC_GRP_NMI, 1), ATH10K_HTC_SVC_ID_HTT_DATA_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 0), ATH10K_HTC_SVC_ID_HTT_DATA2_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 1), ATH10K_HTC_SVC_ID_HTT_DATA3_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 2), ATH10K_HTC_SVC_ID_HTT_IPA_MSG = SVC(ATH10K_IPA_SERVICE_GROUP, 0), ATH10K_HTC_SVC_ID_HTT_LOG_MSG = SVC(ATH10K_LOG_SERVICE_GROUP, 0), /* raw stream service (i.e. flash, tcmd, calibration apps) */ ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS = SVC(ATH10K_HTC_SVC_GRP_TEST, 0), }; Loading
drivers/net/wireless/ath/ath10k/snoc.c 0 → 100644 +704 −0 Original line number Diff line number Diff line /* Copyright (c) 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <linux/module.h> #include <linux/kernel.h> #include "debug.h" #include "hif.h" #include "htc.h" #include "ce.h" #include "snoc.h" #include <soc/qcom/icnss.h> #include <linux/of.h> #include <linux/platform_device.h> static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); static struct ce_attr host_ce_config_wlan[] = { /* CE0: host->target HTC control streams */ { .flags = CE_ATTR_FLAGS, .src_nentries = 16, .src_sz_max = 2048, .dest_nentries = 0, .send_cb = ath10k_snoc_htc_tx_cb, }, /* CE1: target->host HTT + HTC control */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 512, .recv_cb = ath10k_snoc_htt_htc_rx_cb, }, /* CE2: target->host WMI */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 64, .recv_cb = ath10k_snoc_htc_rx_cb, }, /* CE3: host->target WMI */ { .flags = CE_ATTR_FLAGS, .src_nentries = 32, .src_sz_max = 2048, .dest_nentries = 0, .send_cb = ath10k_snoc_htc_tx_cb, }, /* CE4: host->target HTT */ { .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, .src_nentries = 256, .src_sz_max = 256, .dest_nentries = 0, .send_cb = ath10k_snoc_htt_tx_cb, }, /* CE5: target->host HTT (ipa_uc->target ) */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 512, .dest_nentries = 512, .recv_cb = ath10k_snoc_htt_rx_cb, }, /* CE6: target autonomous hif_memcpy */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 0, .dest_nentries = 0, }, /* CE7: ce_diag, the Diagnostic Window */ { .flags = CE_ATTR_FLAGS, .src_nentries = 2, .src_sz_max = 2048, .dest_nentries = 2, }, /* CE8: Target to uMC */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 128, }, /* CE9 target->host HTT */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 512, .recv_cb = ath10k_snoc_htt_htc_rx_cb, }, /* CE10: target->host HTT */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 512, .recv_cb = ath10k_snoc_htt_htc_rx_cb, }, /* CE11: target -> host PKTLOG */ { .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, .dest_nentries = 512, .recv_cb = ath10k_snoc_htt_htc_rx_cb, }, }; static struct ce_pipe_config target_ce_config_wlan[] = { /* CE0: host->target HTC control and raw streams */ { .pipenum = __cpu_to_le32(0), .pipedir = __cpu_to_le32(PIPEDIR_OUT), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE1: target->host HTT + HTC control */ { .pipenum = __cpu_to_le32(1), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE2: target->host WMI */ { .pipenum = __cpu_to_le32(2), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(64), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE3: host->target WMI */ { .pipenum = __cpu_to_le32(3), .pipedir = __cpu_to_le32(PIPEDIR_OUT), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE4: host->target HTT */ { .pipenum = __cpu_to_le32(4), .pipedir = __cpu_to_le32(PIPEDIR_OUT), .nentries = __cpu_to_le32(256), .nbytes_max = __cpu_to_le32(256), .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), .reserved = __cpu_to_le32(0), }, /* CE5: target->host HTT (HIF->HTT) */ { .pipenum = __cpu_to_le32(5), .pipedir = __cpu_to_le32(PIPEDIR_OUT), .nentries = __cpu_to_le32(1024), .nbytes_max = __cpu_to_le32(64), .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), .reserved = __cpu_to_le32(0), }, /* CE6: Reserved for target autonomous hif_memcpy */ { .pipenum = __cpu_to_le32(6), .pipedir = __cpu_to_le32(PIPEDIR_INOUT), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(16384), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE7 used only by Host */ { .pipenum = __cpu_to_le32(7), .pipedir = __cpu_to_le32(4), .nentries = __cpu_to_le32(0), .nbytes_max = __cpu_to_le32(0), .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), .reserved = __cpu_to_le32(0), }, /* CE8 Target to uMC */ { .pipenum = __cpu_to_le32(8), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(0), .reserved = __cpu_to_le32(0), }, /* CE9 target->host HTT */ { .pipenum = __cpu_to_le32(9), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE10 target->host HTT */ { .pipenum = __cpu_to_le32(10), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, /* CE11 target autonomous qcache memcpy */ { .pipenum = __cpu_to_le32(11), .pipedir = __cpu_to_le32(PIPEDIR_IN), .nentries = __cpu_to_le32(32), .nbytes_max = __cpu_to_le32(2048), .flags = __cpu_to_le32(CE_ATTR_FLAGS), .reserved = __cpu_to_le32(0), }, }; static struct service_to_pipe target_service_to_ce_map_wlan[] = { { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(3), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(0), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { /* not used */ __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(0), }, { /* not used */ __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(2), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ __cpu_to_le32(4), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(1), }, { __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_IPA_MSG), __cpu_to_le32(PIPEDIR_OUT),/* IPA service */ __cpu_to_le32(5), }, { /* in = DL = target -> host */ __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(9), }, { /* in = DL = target -> host */ __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(10), }, { /* in = DL = target -> host pktlog */ __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG), __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ __cpu_to_le32(11), }, /* (Additions here) */ { /* must be last */ __cpu_to_le32(0), __cpu_to_le32(0), __cpu_to_le32(0), }, }; void ath10k_snoc_write32(void *ar, u32 offset, u32 value) { } u32 ath10k_snoc_read32(void *ar, u32 offset) { u32 val = 0; return val; } static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe *pipe) { struct ath10k *ar = pipe->hif_ce_state; struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; struct sk_buff *skb; dma_addr_t paddr; int ret; skb = dev_alloc_skb(pipe->buf_sz); if (!skb) return -ENOMEM; WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); paddr = dma_map_single(ar->dev, skb->data, skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); if (unlikely(dma_mapping_error(ar->dev, paddr))) { ath10k_warn(ar, "failed to dma map snoc rx buf\n"); dev_kfree_skb_any(skb); return -EIO; } ATH10K_SKB_RXCB(skb)->paddr = paddr; spin_lock_bh(&ar_snoc->ce_lock); ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr); spin_unlock_bh(&ar_snoc->ce_lock); if (ret) { dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); dev_kfree_skb_any(skb); return ret; } return 0; } static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe *pipe) { struct ath10k *ar = pipe->hif_ce_state; struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; int ret, num; if (pipe->buf_sz == 0) return; if (!ce_pipe->dest_ring) return; spin_lock_bh(&ar_snoc->ce_lock); num = __ath10k_ce_rx_num_free_bufs(ce_pipe); spin_unlock_bh(&ar_snoc->ce_lock); while (num--) { ret = __ath10k_snoc_rx_post_buf(pipe); if (ret) { if (ret == -ENOSPC) break; ath10k_warn(ar, "failed to post rx buf: %d\n", ret); mod_timer(&ar_snoc->rx_post_retry, jiffies + ATH10K_SNOC_RX_POST_RETRY_MS); break; } } } static void ath10k_snoc_rx_post(struct ath10k *ar) { struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); int i; for (i = 0; i < CE_COUNT; i++) ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]); } static void ath10k_snoc_rx_replenish_retry(unsigned long ptr) { struct ath10k *ar = (void *)ptr; ath10k_snoc_rx_post(ar); } static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state) { struct ath10k *ar = ce_state->ar; struct sk_buff_head list; struct sk_buff *skb; __skb_queue_head_init(&list); while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { if (!skb) continue; __skb_queue_tail(&list, skb); } while ((skb = __skb_dequeue(&list))) ath10k_htc_tx_completion_handler(ar, skb); } static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe *ce_state, void (*callback)(struct ath10k *ar, struct sk_buff *skb)) { struct ath10k *ar = ce_state->ar; struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); struct ath10k_snoc_pipe *pipe_info = &ar_snoc->pipe_info[ce_state->id]; struct sk_buff *skb; struct sk_buff_head list; void *transfer_context; unsigned int nbytes, max_nbytes; __skb_queue_head_init(&list); while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, &nbytes) == 0) { skb = transfer_context; max_nbytes = skb->len + skb_tailroom(skb); dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, max_nbytes, DMA_FROM_DEVICE); if (unlikely(max_nbytes < nbytes)) { ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", nbytes, max_nbytes); dev_kfree_skb_any(skb); continue; } skb_put(skb, nbytes); __skb_queue_tail(&list, skb); } while ((skb = __skb_dequeue(&list))) { ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc rx ce pipe %d len %d\n", ce_state->id, skb->len); callback(ar, skb); } ath10k_snoc_rx_post_pipe(pipe_info); } static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state) { ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); } static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) { /* CE4 polling needs to be done whenever CE pipe which transports * HTT Rx (target->host) is processed. */ ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE); ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); } static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state) { struct ath10k *ar = ce_state->ar; struct sk_buff *skb; while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { /* no need to call tx completion for NULL pointers */ if (!skb) continue; dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, skb->len, DMA_TO_DEVICE); ath10k_htt_hif_tx_complete(ar, skb); } } static void ath10k_snoc_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) { skb_pull(skb, sizeof(struct ath10k_htc_hdr)); ath10k_htt_t2h_msg_handler(ar, skb); } static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state) { /* CE4 polling needs to be done whenever CE pipe which transports * HTT Rx (target->host) is processed. */ ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE); ath10k_snoc_process_rx_cb(ce_state, ath10k_snoc_htt_rx_deliver); } static int ath10k_snoc_hif_tx_sg(struct ath10k *ar, u8 pipe_id, struct ath10k_hif_sg_item *items, int n_items) { return 0; } static u16 ath10k_snoc_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) { return 0; } static void ath10k_snoc_hif_send_complete_check(struct ath10k *ar, u8 pipe, int force) { } static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, u8 *ul_pipe, u8 *dl_pipe) { return 0; } static void ath10k_snoc_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe, u8 *dl_pipe) { } static void ath10k_snoc_hif_stop(struct ath10k *ar) { } static void ath10k_snoc_hif_power_down(struct ath10k *ar) { } static int ath10k_snoc_hif_start(struct ath10k *ar) { return 0; } static int ath10k_snoc_hif_power_up(struct ath10k *ar) { return 0; } static const struct ath10k_hif_ops ath10k_snoc_hif_ops = { .tx_sg = ath10k_snoc_hif_tx_sg, .start = ath10k_snoc_hif_start, .stop = ath10k_snoc_hif_stop, .map_service_to_pipe = ath10k_snoc_hif_map_service_to_pipe, .get_default_pipe = ath10k_snoc_hif_get_default_pipe, .send_complete_check = ath10k_snoc_hif_send_complete_check, .get_free_queue_number = ath10k_snoc_hif_get_free_queue_number, .power_up = ath10k_snoc_hif_power_up, .power_down = ath10k_snoc_hif_power_down, .read32 = ath10k_snoc_read32, .write32 = ath10k_snoc_write32, }; static int ath10k_snoc_probe(struct platform_device *pdev) { int ret = 0; struct ath10k *ar; struct ath10k_snoc *ar_snoc; enum ath10k_hw_rev hw_rev; struct device *dev; dev = &pdev->dev; hw_rev = ATH10K_HW_WCN3990; ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(37)); ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC, hw_rev, &ath10k_snoc_hif_ops); if (!ar) { dev_err(dev, "failed to allocate core\n"); return -ENOMEM; } ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 probed\n", __func__); return ret; } static int ath10k_snoc_remove(struct platform_device *pdev) { struct ath10k *ar = platform_get_drvdata(pdev); struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); if (!ar) return -EINVAL; if (!ar_snoc) return -EINVAL; ath10k_core_destroy(ar); ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 removed\n", __func__); return 0; } static const struct of_device_id ath10k_snoc_dt_match[] = { {.compatible = "qcom,wcn3990-wifi"}, {} }; MODULE_DEVICE_TABLE(of, ath10k_snoc_dt_match); static struct platform_driver ath10k_snoc_driver = { .probe = ath10k_snoc_probe, .remove = ath10k_snoc_remove, .driver = { .name = "ath10k_snoc", .owner = THIS_MODULE, .of_match_table = ath10k_snoc_dt_match, }, }; static int __init ath10k_snoc_init(void) { int ret; ret = platform_driver_register(&ath10k_snoc_driver); if (ret) pr_err("failed to register ath10k snoc driver: %d\n", ret); return ret; } module_init(ath10k_snoc_init); static void __exit ath10k_snoc_exit(void) { platform_driver_unregister(&ath10k_snoc_driver); } module_exit(ath10k_snoc_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices");
drivers/net/wireless/ath/ath10k/snoc.h 0 → 100644 +204 −0 Original line number Diff line number Diff line /* Copyright (c) 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef _SNOC_H_ #define _SNOC_H_ #include "hw.h" #include "ce.h" #include "pci.h" #define ATH10K_SNOC_RX_POST_RETRY_MS 50 #define CE_POLL_PIPE 4 /* struct snoc_state: SNOC target state * @pipe_cfg_addr: pipe configuration address * @svc_to_pipe_map: pipe services */ struct snoc_state { u32 pipe_cfg_addr; u32 svc_to_pipe_map; }; /* struct ath10k_snoc_pipe: SNOC pipe configuration * @ath10k_ce_pipe: pipe handle * @pipe_num: pipe number * @hif_ce_state: pointer to ce state * @buf_sz: buffer size * @pipe_lock: pipe lock * @ar_snoc: snoc private structure * @intr: tasklet structure */ struct ath10k_snoc_pipe { struct ath10k_ce_pipe *ce_hdl; u8 pipe_num; struct ath10k *hif_ce_state; size_t buf_sz; /* protect ce info */ spinlock_t pipe_lock; struct ath10k_snoc *ar_snoc; struct tasklet_struct intr; }; /* struct ath10k_snoc_supp_chip: supported chip set * @dev_id: device id * @rev_id: revison id */ struct ath10k_snoc_supp_chip { u32 dev_id; u32 rev_id; }; /* struct ath10k_snoc_info: SNOC info struct * @v_addr: base virtual address * @p_addr: base physical address * @chip_id: chip id * @chip_family: chip family * @board_id: board id * @soc_id: soc id * @fw_version: fw version */ struct ath10k_snoc_info { void __iomem *v_addr; phys_addr_t p_addr; u32 chip_id; u32 chip_family; u32 board_id; u32 soc_id; u32 fw_version; }; /* struct ath10k_target_info: SNOC target info * @target_version: target version * @target_type: target type * @target_revision: target revision * @soc_version: target soc version */ struct ath10k_target_info { u32 target_version; u32 target_type; u32 target_revision; u32 soc_version; }; /* struct ath10k_snoc: SNOC info struct * @dev: device structure * @ar:ath10k base structure * @mem: mem base virtual address * @mem_pa: mem base physical address * @target_info: snoc target info * @mem_len: mempry map length * @intr_tq: rx tasklet handle * @pipe_info: pipe info struct * @ce_lock: protect ce structures * @ce_states: maps ce id to ce state * @rx_post_retry: rx buffer post processing timer * @vaddr_rri_on_ddr: virtual address for RRI * @is_driver_probed: flag to indicate driver state */ struct ath10k_snoc { struct device *dev; struct ath10k *ar; void __iomem *mem; dma_addr_t mem_pa; struct ath10k_target_info target_info; size_t mem_len; struct tasklet_struct intr_tq; struct ath10k_snoc_pipe pipe_info[CE_COUNT_MAX]; /* protects CE info */ spinlock_t ce_lock; struct ath10k_ce_pipe ce_states[CE_COUNT_MAX]; struct timer_list rx_post_retry; u32 *vaddr_rri_on_ddr; bool is_driver_probed; }; /* struct ath10k_ce_tgt_pipe_cfg: target pipe configuration * @pipe_num: pipe number * @pipe_dir: pipe direction * @nentries: entries in pipe * @nbytes_max: pipe max size * @flags: pipe flags * @reserved: reserved */ struct ath10k_ce_tgt_pipe_cfg { u32 pipe_num; u32 pipe_dir; u32 nentries; u32 nbytes_max; u32 flags; u32 reserved; }; /* struct ath10k_ce_svc_pipe_cfg: service pipe configuration * @service_id: target version * @pipe_dir: pipe direction * @pipe_num: pipe number */ struct ath10k_ce_svc_pipe_cfg { u32 service_id; u32 pipe_dir; u32 pipe_num; }; /* struct ath10k_shadow_reg_cfg: shadow register configuration * @ce_id: copy engine id * @reg_offset: offset to copy engine */ struct ath10k_shadow_reg_cfg { u16 ce_id; u16 reg_offset; }; /* struct ath10k_wlan_enable_cfg: wlan enable configuration * @num_ce_tgt_cfg: no of ce target configuration * @ce_tgt_cfg: target ce configuration * @num_ce_svc_pipe_cfg: no of ce service configuration * @ce_svc_cfg: ce service configuration * @num_shadow_reg_cfg: no of shadow registers * @shadow_reg_cfg: shadow register configuration */ struct ath10k_wlan_enable_cfg { u32 num_ce_tgt_cfg; struct ath10k_ce_tgt_pipe_cfg *ce_tgt_cfg; u32 num_ce_svc_pipe_cfg; struct ath10k_ce_svc_pipe_cfg *ce_svc_cfg; u32 num_shadow_reg_cfg; struct ath10k_shadow_reg_cfg *shadow_reg_cfg; }; /* enum ath10k_driver_mode: ath10k driver mode * @ATH10K_MISSION: mission mode * @ATH10K_FTM: ftm mode * @ATH10K_EPPING: epping mode * @ATH10K_OFF: off mode */ enum ath10k_driver_mode { ATH10K_MISSION, ATH10K_FTM, ATH10K_EPPING, ATH10K_OFF }; static inline struct ath10k_snoc *ath10k_snoc_priv(struct ath10k *ar) { return (struct ath10k_snoc *)ar->drv_priv; } void ath10k_snoc_write32(void *ar, u32 offset, u32 value); void ath10k_snoc_soc_write32(struct ath10k *ar, u32 addr, u32 val); void ath10k_snoc_reg_write32(struct ath10k *ar, u32 addr, u32 val); u32 ath10k_snoc_read32(void *ar, u32 offset); u32 ath10k_snoc_soc_read32(struct ath10k *ar, u32 addr); u32 ath10k_snoc_reg_read32(struct ath10k *ar, u32 addr); #endif /* _SNOC_H_ */
