Loading Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt +0 −1 Original line number Diff line number Diff line Loading @@ -118,7 +118,6 @@ First Level Node - FG Gen3 device Definition: Specifies the source of sense resistor. Allowed values are: 0 - Rsense is from Battery FET 1 - Rsense is external 2 - Rsense is Battery FET and SMB Option 2 can be used only when a parallel charger is present. If this property is not specified, then the Loading drivers/power/supply/qcom/fg-reg.h +1 −2 Original line number Diff line number Diff line /* Copyright (c) 2016, The Linux Foundation. All rights reserved. /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -211,7 +211,6 @@ #define ADC_BITSTREAM_INV_BIT BIT(4) #define SOURCE_SELECT_MASK GENMASK(1, 0) #define SRC_SEL_BATFET 0x0 #define SRC_SEL_RSENSE 0x1 #define SRC_SEL_BATFET_SMB 0x2 #define SRC_SEL_RESERVED 0x3 Loading Loading
Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt +0 −1 Original line number Diff line number Diff line Loading @@ -118,7 +118,6 @@ First Level Node - FG Gen3 device Definition: Specifies the source of sense resistor. Allowed values are: 0 - Rsense is from Battery FET 1 - Rsense is external 2 - Rsense is Battery FET and SMB Option 2 can be used only when a parallel charger is present. If this property is not specified, then the Loading
drivers/power/supply/qcom/fg-reg.h +1 −2 Original line number Diff line number Diff line /* Copyright (c) 2016, The Linux Foundation. All rights reserved. /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -211,7 +211,6 @@ #define ADC_BITSTREAM_INV_BIT BIT(4) #define SOURCE_SELECT_MASK GENMASK(1, 0) #define SRC_SEL_BATFET 0x0 #define SRC_SEL_RSENSE 0x1 #define SRC_SEL_BATFET_SMB 0x2 #define SRC_SEL_RESERVED 0x3 Loading