Loading drivers/video/fbdev/msm/mdss.h +1 −0 Original line number Diff line number Diff line Loading @@ -193,6 +193,7 @@ enum mdss_qos_settings { MDSS_QOS_REMAPPER, MDSS_QOS_IB_NOCR, MDSS_QOS_WB2_WRITE_GATHER_EN, MDSS_QOS_WB_QOS, MDSS_QOS_MAX, }; Loading drivers/video/fbdev/msm/mdss_mdp.c +2 −0 Original line number Diff line number Diff line Loading @@ -1992,6 +1992,8 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) set_bit(MDSS_QOS_PER_PIPE_IB, mdata->mdss_qos_map); set_bit(MDSS_QOS_REMAPPER, mdata->mdss_qos_map); set_bit(MDSS_QOS_TS_PREFILL, mdata->mdss_qos_map); set_bit(MDSS_QOS_WB_QOS, mdata->mdss_qos_map); set_bit(MDSS_QOS_OVERHEAD_FACTOR, mdata->mdss_qos_map); set_bit(MDSS_QOS_CDP, mdata->mdss_qos_map); /* cdp supported */ mdata->enable_cdp = false; /* disable cdp */ Loading drivers/video/fbdev/msm/mdss_mdp.h +6 −1 Original line number Diff line number Diff line Loading @@ -122,6 +122,11 @@ */ #define MDSS_MDP_DS_OVERFETCH_SIZE 5 #define QOS_LUT_NRT_READ 0x0 #define QOS_LUT_CWB_READ 0xe4000000 #define PANIC_LUT_NRT_READ 0x0 #define ROBUST_LUT_NRT_READ 0xFFFF /* hw cursor can only be setup in highest mixer stage */ #define HW_CURSOR_STAGE(mdata) \ (((mdata)->max_target_zorder + MDSS_MDP_STAGE_0) - 1) Loading Loading @@ -407,7 +412,7 @@ struct mdss_mdp_cwb { struct list_head data_queue; int valid; u32 wb_idx; struct mdp_output_layer *layer; struct mdp_output_layer layer; void *priv_data; struct msm_sync_pt_data cwb_sync_pt_data; struct blocking_notifier_head notifier_head; Loading drivers/video/fbdev/msm/mdss_mdp_ctl.c +8 −3 Original line number Diff line number Diff line Loading @@ -3424,6 +3424,7 @@ int mdss_mdp_cwb_setup(struct mdss_mdp_ctl *ctl) mutex_lock(&cwb->queue_lock); cwb_data = list_first_entry_or_null(&cwb->data_queue, struct mdss_mdp_wb_data, next); __list_del_entry(&cwb_data->next); mutex_unlock(&cwb->queue_lock); if (cwb_data == NULL) { pr_err("no output buffer for cwb\n"); Loading Loading @@ -3453,14 +3454,14 @@ int mdss_mdp_cwb_setup(struct mdss_mdp_ctl *ctl) sctl->opmode |= MDSS_MDP_CTL_OP_WFD_MODE; /* Select CWB data point */ data_point = (cwb->layer->flags & MDP_COMMIT_CWB_DSPP) ? 0x4 : 0; data_point = (cwb->layer.flags & MDP_COMMIT_CWB_DSPP) ? 0x4 : 0; writel_relaxed(data_point, mdata->mdp_base + mdata->ppb_ctl[2]); if (sctl) writel_relaxed(data_point + 1, mdata->mdp_base + mdata->ppb_ctl[3]); /* Flush WB */ ctl->flush_bits |= BIT(16); /* Flush WB and CTL */ ctl->flush_bits |= BIT(16) | BIT(17); opmode = mdss_mdp_ctl_read(ctl, MDSS_MDP_REG_CTL_TOP) | ctl->opmode; mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_TOP, opmode); Loading @@ -3469,6 +3470,10 @@ int mdss_mdp_cwb_setup(struct mdss_mdp_ctl *ctl) sctl->opmode; mdss_mdp_ctl_write(sctl, MDSS_MDP_REG_CTL_TOP, opmode); } /* Increase commit count to signal CWB release fence */ atomic_inc(&cwb->cwb_sync_pt_data.commit_cnt); goto cwb_setup_done; cwb_setup_fail: Loading drivers/video/fbdev/msm/mdss_mdp_hwio.h +4 −0 Original line number Diff line number Diff line Loading @@ -541,6 +541,10 @@ enum mdss_mdp_writeback_index { #define MDSS_MDP_REG_WB_N16_INIT_PHASE_Y_C12 0x06C #define MDSS_MDP_REG_WB_OUT_SIZE 0x074 #define MDSS_MDP_REG_WB_ALPHA_X_VALUE 0x078 #define MDSS_MDP_REG_WB_DANGER_LUT 0x084 #define MDSS_MDP_REG_WB_SAFE_LUT 0x088 #define MDSS_MDP_REG_WB_CREQ_LUT 0x08c #define MDSS_MDP_REG_WB_QOS_CTRL 0x090 #define MDSS_MDP_REG_WB_CSC_BASE 0x260 #define MDSS_MDP_REG_WB_DST_ADDR_SW_STATUS 0x2B0 #define MDSS_MDP_REG_WB_CDP_CTRL 0x2B4 Loading Loading
drivers/video/fbdev/msm/mdss.h +1 −0 Original line number Diff line number Diff line Loading @@ -193,6 +193,7 @@ enum mdss_qos_settings { MDSS_QOS_REMAPPER, MDSS_QOS_IB_NOCR, MDSS_QOS_WB2_WRITE_GATHER_EN, MDSS_QOS_WB_QOS, MDSS_QOS_MAX, }; Loading
drivers/video/fbdev/msm/mdss_mdp.c +2 −0 Original line number Diff line number Diff line Loading @@ -1992,6 +1992,8 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) set_bit(MDSS_QOS_PER_PIPE_IB, mdata->mdss_qos_map); set_bit(MDSS_QOS_REMAPPER, mdata->mdss_qos_map); set_bit(MDSS_QOS_TS_PREFILL, mdata->mdss_qos_map); set_bit(MDSS_QOS_WB_QOS, mdata->mdss_qos_map); set_bit(MDSS_QOS_OVERHEAD_FACTOR, mdata->mdss_qos_map); set_bit(MDSS_QOS_CDP, mdata->mdss_qos_map); /* cdp supported */ mdata->enable_cdp = false; /* disable cdp */ Loading
drivers/video/fbdev/msm/mdss_mdp.h +6 −1 Original line number Diff line number Diff line Loading @@ -122,6 +122,11 @@ */ #define MDSS_MDP_DS_OVERFETCH_SIZE 5 #define QOS_LUT_NRT_READ 0x0 #define QOS_LUT_CWB_READ 0xe4000000 #define PANIC_LUT_NRT_READ 0x0 #define ROBUST_LUT_NRT_READ 0xFFFF /* hw cursor can only be setup in highest mixer stage */ #define HW_CURSOR_STAGE(mdata) \ (((mdata)->max_target_zorder + MDSS_MDP_STAGE_0) - 1) Loading Loading @@ -407,7 +412,7 @@ struct mdss_mdp_cwb { struct list_head data_queue; int valid; u32 wb_idx; struct mdp_output_layer *layer; struct mdp_output_layer layer; void *priv_data; struct msm_sync_pt_data cwb_sync_pt_data; struct blocking_notifier_head notifier_head; Loading
drivers/video/fbdev/msm/mdss_mdp_ctl.c +8 −3 Original line number Diff line number Diff line Loading @@ -3424,6 +3424,7 @@ int mdss_mdp_cwb_setup(struct mdss_mdp_ctl *ctl) mutex_lock(&cwb->queue_lock); cwb_data = list_first_entry_or_null(&cwb->data_queue, struct mdss_mdp_wb_data, next); __list_del_entry(&cwb_data->next); mutex_unlock(&cwb->queue_lock); if (cwb_data == NULL) { pr_err("no output buffer for cwb\n"); Loading Loading @@ -3453,14 +3454,14 @@ int mdss_mdp_cwb_setup(struct mdss_mdp_ctl *ctl) sctl->opmode |= MDSS_MDP_CTL_OP_WFD_MODE; /* Select CWB data point */ data_point = (cwb->layer->flags & MDP_COMMIT_CWB_DSPP) ? 0x4 : 0; data_point = (cwb->layer.flags & MDP_COMMIT_CWB_DSPP) ? 0x4 : 0; writel_relaxed(data_point, mdata->mdp_base + mdata->ppb_ctl[2]); if (sctl) writel_relaxed(data_point + 1, mdata->mdp_base + mdata->ppb_ctl[3]); /* Flush WB */ ctl->flush_bits |= BIT(16); /* Flush WB and CTL */ ctl->flush_bits |= BIT(16) | BIT(17); opmode = mdss_mdp_ctl_read(ctl, MDSS_MDP_REG_CTL_TOP) | ctl->opmode; mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_TOP, opmode); Loading @@ -3469,6 +3470,10 @@ int mdss_mdp_cwb_setup(struct mdss_mdp_ctl *ctl) sctl->opmode; mdss_mdp_ctl_write(sctl, MDSS_MDP_REG_CTL_TOP, opmode); } /* Increase commit count to signal CWB release fence */ atomic_inc(&cwb->cwb_sync_pt_data.commit_cnt); goto cwb_setup_done; cwb_setup_fail: Loading
drivers/video/fbdev/msm/mdss_mdp_hwio.h +4 −0 Original line number Diff line number Diff line Loading @@ -541,6 +541,10 @@ enum mdss_mdp_writeback_index { #define MDSS_MDP_REG_WB_N16_INIT_PHASE_Y_C12 0x06C #define MDSS_MDP_REG_WB_OUT_SIZE 0x074 #define MDSS_MDP_REG_WB_ALPHA_X_VALUE 0x078 #define MDSS_MDP_REG_WB_DANGER_LUT 0x084 #define MDSS_MDP_REG_WB_SAFE_LUT 0x088 #define MDSS_MDP_REG_WB_CREQ_LUT 0x08c #define MDSS_MDP_REG_WB_QOS_CTRL 0x090 #define MDSS_MDP_REG_WB_CSC_BASE 0x260 #define MDSS_MDP_REG_WB_DST_ADDR_SW_STATUS 0x2B0 #define MDSS_MDP_REG_WB_CDP_CTRL 0x2B4 Loading