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Commit de04dbd9 authored by Amey Telawane's avatar Amey Telawane
Browse files

ARM: dts: msm: add jtag, hwevent and csr nodes for falcon 



Add etm save retore nodes which saves etm
values across power collapse. Hwevent is
used to collect hardware events.

Change-Id: I329aa4084c0983f066cdd06455c3d69e255a420c
CRs-fixed: 1056777
Signed-off-by: default avatarAmey Telawane <ameyt@codeaurora.org>
parent c15fe981

arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi

+155 −1
Original line number Diff line number Diff line
@@ -43,10 +43,18 @@ 
	};



	replicator: replicator@6046000 {

		compatible = "arm,coresight-replicator";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b909>;



		reg = <0x6046000 0x1000>;

		reg-names = "replicator-base";



		coresight-name = "coresight-replicator";



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "apb_pclk", "core_a_clk";



		ports{

			#address-cells = <1>;

			#size-cells = <0>;
@@ -188,6 +196,14 @@ 
					remote-endpoint = <&stm_out_funnel_in0>;

				};

			};

			port@4 {

				reg = <0>;

				funnel_in0_in_rpm_etm0: endpoint {

					slave-mode;

					remote-endpoint =

						<&rpm_etm0_out_funnel_in0>;

				};

			};

		};

	};
@@ -239,6 +255,14 @@ 
					    <&funnel_apss_merg_out_funnel_in1>;

				};

			};

			port@4 {

				reg = <4>;

				funnel_in1_in_turing_etm0: endpoint {

					slave-mode;

					remote-endpoint =

					    <&turing_etm0_out_funnel_in1>;

				};

			};

		};

	};
@@ -599,6 +623,10 @@ 
		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";



		qcom,cti-gpio-trigout = <4>;

		pinctrl-names = "cti-trigout-pctrl";

		pinctrl-0 = <&trigout_b>;

	};



	cti3: cti@6013000 {
@@ -765,6 +793,8 @@ 
		coresight-name = "coresight-cti-cpu0";

		cpu = <&CPU0>;



		qcom,cti-save;



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";
@@ -778,6 +808,8 @@ 
		coresight-name = "coresight-cti-cpu1";

		cpu = <&CPU1>;



		qcom,cti-save;



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";
@@ -791,6 +823,8 @@ 
		coresight-name = "coresight-cti-cpu2";

		cpu = <&CPU2>;



		qcom,cti-save;



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";
@@ -804,6 +838,8 @@ 
		coresight-name = "coresight-cti-cpu3";

		cpu = <&CPU3>;



		qcom,cti-save;



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";
@@ -817,6 +853,8 @@ 
		coresight-name = "coresight-cti-cpu4";

		cpu = <&CPU4>;



		qcom,cti-save;



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";
@@ -830,6 +868,8 @@ 
		coresight-name = "coresight-cti-cpu5";

		cpu = <&CPU5>;



		qcom,cti-save;



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";
@@ -843,6 +883,8 @@ 
		coresight-name = "coresight-cti-cpu6";

		cpu = <&CPU6>;



		qcom,cti-save;



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";
@@ -856,6 +898,8 @@ 
		coresight-name = "coresight-cti-cpu7";

		cpu = <&CPU7>;



		qcom,cti-save;



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";
@@ -1582,6 +1626,22 @@ 
						<&funnel_wcss_out_funnel_dlct>;

				};

			};

			port@4 {

				reg = <1>;

				funnel_dlct_in_audio_etm0: endpoint {

					slave-mode;

					remote-endpoint =

						<&audio_etm0_out_funnel_dlct>;

				};

			};

			port@5 {

				reg = <2>;

				funnel_dlct_in_modem_etm0: endpoint {

					slave-mode;

					remote-endpoint =

						<&modem_etm0_out_funnel_dlct>;

				};

			};

		};

	};
@@ -1603,6 +1663,100 @@ 
		};

	};



	hwevent: hwevent@158000 {

		compatible = "qcom,coresight-hwevent";

		reg = <0x158000 0x80>,

		      <0x17091000 0x80>,

		      <0x1730200c 0x4>,

		      <0xc90137c 0x4>,

		      <0xc828018 0x80>,

		      <0x1c00058 0x80>,

		      <0x5e02038 0x4>,

		      <0x5e02028 0x10>,

		      <0x1fcb360 0x80>,

		      <0x1fcb760 0x80>,

		      <0x1fcbf60 0x80>,

		      <0xa8f8860 0x4>,

		      <0x500c260 0x4>,

		      <0x500d040 0x4>,

		      <0x1da6400 0x80>;

		reg-names = "gcc-ctrl", "lpass-stm", "lpass-qdsp", "mdss-mdp",

			    "mdss-misc", "pcie0-hwev", "ssc-en", "ssc-hwev",

			    "tcsr-qdss", "tcsr-mss0", "tcsr-mss1", "usb-ctrl",

			    "vbif-stm", "vbif-stm-en", "ufs-mux";



		coresight-name = "coresight-hwevent";



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>,

			 <&clock_mmss MMSS_MISC_AHB_CLK>;

		clock-names = "core_clk", "core_a_clk", "core_mmss_clk";



		qcom,hwevent-clks = "core_mmss_clk";

	};



	csr: csr@6001000 {

		compatible = "qcom,coresight-csr";

		reg = <0x6001000 0x1000>;

		reg-names = "csr-base";



		coresight-name = "coresight-csr";



		qcom,blk-size = <1>;

	};



	modem_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-name = "coresight-modem-etm0";

		qcom,inst-id = <2>;



		port{

			modem_etm0_out_funnel_dlct: endpoint {

				remote-endpoint = <&funnel_dlct_in_modem_etm0>;

			};

		};

	};



	audio_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-name = "coresight-audio-etm0";

		qcom,inst-id = <5>;



		port{

			audio_etm0_out_funnel_dlct: endpoint {

				remote-endpoint = <&funnel_dlct_in_audio_etm0>;

			};

		};

	};



	rpm_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-name = "coresight-rpm-etm0";

		qcom,inst-id = <4>;



		port{

			rpm_etm0_out_funnel_in0: endpoint {

				remote-endpoint = <&funnel_in0_in_rpm_etm0>;

			};

		};

	};



	turing_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-name = "coresight-turing-etm0";

		qcom,inst-id = <13>;



		port{

			turing_etm0_out_funnel_in1: endpoint {

				remote-endpoint = <&funnel_in1_in_turing_etm0>;

			};

		};

	};



	funnel_wcss: funnel@719e000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b908>;

arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -49,6 +49,19 @@ 
			};

		};



		trigout_b: trigout_b {

			mux {

				pins = "gpio12";

				function = "qdss_cti1_b";

			};



			config {

				pins = "gpio12";

				drive-strength = <16>;

				bias-disable;

			};

		};



		/* SDC pin type */

		sdc1_clk_on: sdc1_clk_on {

			config {

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+102 −0
Original line number Diff line number Diff line
@@ -1678,6 +1678,108 @@ 


		status = "disabled";

	};



	jtag_fuse: jtagfuse@786040 {

		compatible = "qcom,jtag-fuse-v4";

		reg = <0x786040 0x8>;

		reg-names = "fuse-base";

	};



	jtag_mm0: jtagmm@7840000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7840000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};



	jtag_mm1: jtagmm@7940000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7940000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

	};



	jtag_mm2: jtagmm@7a40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7a40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

	};



	jtag_mm3: jtagmm@7b40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7b40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

	};



	jtag_mm4: jtagmm@7c40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7c40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};



	jtag_mm5: jtagmm@7d40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7d40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

	};



	jtag_mm6: jtagmm@7e40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7e40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

	};



	jtag_mm7: jtagmm@7f40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7f40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_rpmcc RPM_QDSS_CLK>,

			 <&clock_rpmcc RPM_QDSS_A_CLK>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

	};

};



#include "msmfalcon-ion.dtsi"