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Commit dc7a9319 authored by Wang Zhenyu's avatar Wang Zhenyu Committed by Dave Airlie
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drm/i915: Add support for the G33, Q33, and Q35 chipsets. 



These require that the status page be referenced by a pointer in GTT, rather
than phsyical memory.  So, we have the X Server allocate that memory and tell
us the address, instead.

Signed-off-by: default avatarDave Airlie <airlied@linux.ie>
parent 2f4042b1

drivers/char/drm/drm_pciids.h

+3 −0
Original line number Diff line number Diff line
@@ -305,6 +305,9 @@ 
	{0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \

	{0, 0, 0}

drivers/char/drm/i915_dma.c

+70 −17
Original line number Diff line number Diff line
@@ -38,6 +38,10 @@ 
		       dev->pci_device == 0x2A02 || \

		       dev->pci_device == 0x2A12)



#define IS_G33(dev) (dev->pci_device == 0x29b2 || \

		     dev->pci_device == 0x29c2 || \

		     dev->pci_device == 0x29d2)



/* Really want an OS-independent resettable timer.  Would like to have

 * this loop run for (eg) 3 sec, but have the timer reset every time

 * the head pointer changes, so that EBUSY only happens if the ring
@@ -107,6 +111,12 @@ static int i915_dma_cleanup(drm_device_t * dev) 
			I915_WRITE(0x02080, 0x1ffff000);

		}



		if (dev_priv->status_gfx_addr) {

			dev_priv->status_gfx_addr = 0;

			drm_core_ioremapfree(&dev_priv->hws_map, dev);

			I915_WRITE(0x2080, 0x1ffff000);

		}



		drm_free(dev->dev_private, sizeof(drm_i915_private_t),

			 DRM_MEM_DRIVER);
@@ -180,8 +190,9 @@ static int i915_initialize(drm_device_t * dev, 
	dev_priv->allow_batchbuffer = 1;



	/* Program Hardware Status Page */

	dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,

						   0xffffffff);

	if (!IS_G33(dev)) {

		dev_priv->status_page_dmah =

			drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);



		if (!dev_priv->status_page_dmah) {

			dev->dev_private = (void *)dev_priv;
@@ -193,13 +204,10 @@ static int i915_initialize(drm_device_t * dev, 
		dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;



		memset(dev_priv->hw_status_page, 0, PAGE_SIZE);

	DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);



		I915_WRITE(0x02080, dev_priv->dma_status_page);

	}

	DRM_DEBUG("Enabled hardware status page\n");



	dev->dev_private = (void *)dev_priv;



	return 0;

}
@@ -232,6 +240,9 @@ static int i915_dma_resume(drm_device_t * dev) 
	}

	DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);



	if (dev_priv->status_gfx_addr != 0)

		I915_WRITE(0x02080, dev_priv->status_gfx_addr);

	else

		I915_WRITE(0x02080, dev_priv->dma_status_page);

	DRM_DEBUG("Enabled hardware status page\n");
@@ -740,6 +751,47 @@ static int i915_setparam(DRM_IOCTL_ARGS) 
	return 0;

}



static int i915_set_status_page(DRM_IOCTL_ARGS)

{

	DRM_DEVICE;

	drm_i915_private_t *dev_priv = dev->dev_private;

	drm_i915_hws_addr_t hws;



	if (!dev_priv) {

		DRM_ERROR("%s called with no initialization\n", __FUNCTION__);

		return DRM_ERR(EINVAL);

	}

	DRM_COPY_FROM_USER_IOCTL(hws, (drm_i915_hws_addr_t __user *) data,

			sizeof(hws));

	printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws.addr);



	dev_priv->status_gfx_addr = hws.addr & (0x1ffff<<12);



	dev_priv->hws_map.offset = dev->agp->agp_info.aper_base + hws.addr;

	dev_priv->hws_map.size = 4*1024;

	dev_priv->hws_map.type = 0;

	dev_priv->hws_map.flags = 0;

	dev_priv->hws_map.mtrr = 0;



	drm_core_ioremap(&dev_priv->hws_map, dev);

	if (dev_priv->hws_map.handle == NULL) {

		dev->dev_private = (void *)dev_priv;

		i915_dma_cleanup(dev);

		dev_priv->status_gfx_addr = 0;

		DRM_ERROR("can not ioremap virtual address for"

				" G33 hw status page\n");

		return DRM_ERR(ENOMEM);

	}

	dev_priv->hw_status_page = dev_priv->hws_map.handle;



	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);

	I915_WRITE(0x02080, dev_priv->status_gfx_addr);

	DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",

			dev_priv->status_gfx_addr);

	DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);

	return 0;

}



int i915_driver_load(drm_device_t *dev, unsigned long flags)

{

	/* i915 has 4 more counters */
@@ -786,6 +838,7 @@ drm_ioctl_desc_t i915_ioctls[] = { 
	[DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },

	[DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },

	[DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},

	[DRM_IOCTL_NR(DRM_I915_HWS_ADDR)] = {i915_set_status_page, DRM_AUTH},

};



int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);

drivers/char/drm/i915_drm.h

+5 −0
Original line number Diff line number Diff line
@@ -142,6 +142,7 @@ typedef struct _drm_i915_sarea { 
#define DRM_I915_SET_VBLANK_PIPE	0x0d

#define DRM_I915_GET_VBLANK_PIPE	0x0e

#define DRM_I915_VBLANK_SWAP	0x0f

#define DRM_I915_HWS_ADDR	0x11



#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)

#define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -262,4 +263,8 @@ typedef struct drm_i915_vblank_swap { 
	unsigned int sequence;

} drm_i915_vblank_swap_t;



typedef struct drm_i915_hws_addr {

	uint64_t addr;

} drm_i915_hws_addr_t;



#endif				/* _I915_DRM_H_ */

drivers/char/drm/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -91,6 +91,8 @@ typedef struct drm_i915_private { 
	void *hw_status_page;

	dma_addr_t dma_status_page;

	unsigned long counter;

	unsigned int status_gfx_addr;

	drm_local_map_t hws_map;



	unsigned int cpp;

	int back_offset;