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Commit db467fee authored by Marc Zyngier's avatar Marc Zyngier Committed by Greg Kroah-Hartman
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arm64: KVM: Fix decoding of Rt/Rt2 when trapping AArch32 CP accesses 



commit c667186f1c01ca8970c785888868b7ffd74e51ee upstream.

Our 32bit CP14/15 handling inherited some of the ARMv7 code for handling
the trapped system registers, completely missing the fact that the
fields for Rt and Rt2 are now 5 bit wide, and not 4...

Let's fix it, and provide an accessor for the most common Rt case.

Reviewed-by: default avatarChristoffer Dall <cdall@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarChristoffer Dall <cdall@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f08bc4d6

arch/arm64/kvm/sys_regs.c

+3 −3
Original line number Diff line number Diff line
@@ -1054,8 +1054,8 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 
{

	struct sys_reg_params params;

	u32 hsr = kvm_vcpu_get_hsr(vcpu);

	int Rt = (hsr >> 5) & 0xf;

	int Rt2 = (hsr >> 10) & 0xf;

	int Rt = (hsr >> 5) & 0x1f;

	int Rt2 = (hsr >> 10) & 0x1f;



	params.is_aarch32 = true;

	params.is_32bit = false;
@@ -1106,7 +1106,7 @@ static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 
{

	struct sys_reg_params params;

	u32 hsr = kvm_vcpu_get_hsr(vcpu);

	int Rt  = (hsr >> 5) & 0xf;

	int Rt  = (hsr >> 5) & 0x1f;



	params.is_aarch32 = true;

	params.is_32bit = true;