Loading arch/arm/boot/dts/qcom/sdm660-gpu.dtsi +0 −1 Original line number Diff line number Diff line Loading @@ -71,7 +71,6 @@ /* <HZ/12> */ qcom,idle-timeout = <80>; qcom,no-nap; qcom,highest-bank-bit = <14>; Loading drivers/gpu/msm/adreno_a5xx.c +2 −1 Original line number Diff line number Diff line Loading @@ -1639,7 +1639,8 @@ static void a5xx_pwrlevel_change_settings(struct adreno_device *adreno_dev, static void a5xx_clk_set_options(struct adreno_device *adreno_dev, const char *name, struct clk *clk) { if (adreno_is_a540(adreno_dev)) { /* Handle clock settings for GFX PSCBCs */ if (adreno_is_a540(adreno_dev) || adreno_is_a512(adreno_dev)) { if (!strcmp(name, "mem_iface_clk")) { clk_set_flags(clk, CLKFLAG_NORETAIN_PERIPH); clk_set_flags(clk, CLKFLAG_NORETAIN_MEM); Loading Loading
arch/arm/boot/dts/qcom/sdm660-gpu.dtsi +0 −1 Original line number Diff line number Diff line Loading @@ -71,7 +71,6 @@ /* <HZ/12> */ qcom,idle-timeout = <80>; qcom,no-nap; qcom,highest-bank-bit = <14>; Loading
drivers/gpu/msm/adreno_a5xx.c +2 −1 Original line number Diff line number Diff line Loading @@ -1639,7 +1639,8 @@ static void a5xx_pwrlevel_change_settings(struct adreno_device *adreno_dev, static void a5xx_clk_set_options(struct adreno_device *adreno_dev, const char *name, struct clk *clk) { if (adreno_is_a540(adreno_dev)) { /* Handle clock settings for GFX PSCBCs */ if (adreno_is_a540(adreno_dev) || adreno_is_a512(adreno_dev)) { if (!strcmp(name, "mem_iface_clk")) { clk_set_flags(clk, CLKFLAG_NORETAIN_PERIPH); clk_set_flags(clk, CLKFLAG_NORETAIN_MEM); Loading