Loading Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 4 SUBLEVEL = 245 SUBLEVEL = 247 EXTRAVERSION = NAME = Blurry Fish Butt Loading arch/arm/boot/dts/imx50-evk.dts +1 −1 Original line number Diff line number Diff line Loading @@ -66,7 +66,7 @@ MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4 MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84 >; }; Loading arch/arm/boot/dts/imx6qdl-udoo.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -39,7 +39,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-mode = "rgmii-id"; status = "okay"; }; Loading arch/arm64/kernel/psci.c +1 −4 Original line number Diff line number Diff line Loading @@ -71,7 +71,6 @@ static int cpu_psci_cpu_disable(unsigned int cpu) static void cpu_psci_cpu_die(unsigned int cpu) { int ret; /* * There are no known implementations of PSCI actually using the * power state field, pass a sensible default for now. Loading @@ -79,9 +78,7 @@ static void cpu_psci_cpu_die(unsigned int cpu) u32 state = PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT; ret = psci_ops.cpu_off(state); pr_crit("unable to power off CPU%u (%d)\n", cpu, ret); psci_ops.cpu_off(state); } static int cpu_psci_cpu_kill(unsigned int cpu) Loading arch/mips/alchemy/common/clock.c +8 −1 Original line number Diff line number Diff line Loading @@ -151,6 +151,7 @@ static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name, { struct clk_init_data id; struct clk_hw *h; struct clk *clk; h = kzalloc(sizeof(*h), GFP_KERNEL); if (!h) Loading @@ -163,7 +164,13 @@ static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name, id.ops = &alchemy_clkops_cpu; h->init = &id; return clk_register(NULL, h); clk = clk_register(NULL, h); if (IS_ERR(clk)) { pr_err("failed to register clock\n"); kfree(h); } return clk; } /* AUXPLLs ************************************************************/ Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 4 SUBLEVEL = 245 SUBLEVEL = 247 EXTRAVERSION = NAME = Blurry Fish Butt Loading
arch/arm/boot/dts/imx50-evk.dts +1 −1 Original line number Diff line number Diff line Loading @@ -66,7 +66,7 @@ MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4 MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84 >; }; Loading
arch/arm/boot/dts/imx6qdl-udoo.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -39,7 +39,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-mode = "rgmii-id"; status = "okay"; }; Loading
arch/arm64/kernel/psci.c +1 −4 Original line number Diff line number Diff line Loading @@ -71,7 +71,6 @@ static int cpu_psci_cpu_disable(unsigned int cpu) static void cpu_psci_cpu_die(unsigned int cpu) { int ret; /* * There are no known implementations of PSCI actually using the * power state field, pass a sensible default for now. Loading @@ -79,9 +78,7 @@ static void cpu_psci_cpu_die(unsigned int cpu) u32 state = PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT; ret = psci_ops.cpu_off(state); pr_crit("unable to power off CPU%u (%d)\n", cpu, ret); psci_ops.cpu_off(state); } static int cpu_psci_cpu_kill(unsigned int cpu) Loading
arch/mips/alchemy/common/clock.c +8 −1 Original line number Diff line number Diff line Loading @@ -151,6 +151,7 @@ static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name, { struct clk_init_data id; struct clk_hw *h; struct clk *clk; h = kzalloc(sizeof(*h), GFP_KERNEL); if (!h) Loading @@ -163,7 +164,13 @@ static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name, id.ops = &alchemy_clkops_cpu; h->init = &id; return clk_register(NULL, h); clk = clk_register(NULL, h); if (IS_ERR(clk)) { pr_err("failed to register clock\n"); kfree(h); } return clk; } /* AUXPLLs ************************************************************/ Loading