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Commit d9b8af23 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: msm: clock: Vote on MX rail on behalf of MM PLLs on MSMCOBALT 



The multimedia PLLs are all in the MX domain on MSMCOBALT. Replace
voting on the CX rail with voting for MX voltages from the clock
driver. In addition, update the MMPLL7 FMAX table.

CRs-Fixed: 1063153
Change-Id: I296d2b151753be599a1db139e36f5e1eabe76791
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 26745af0

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -745,6 +745,7 @@ 
		reg = <0xc8c0000 0x40000>;

		reg-names = "cc_base";

		vdd_dig-supply = <&pmcobalt_s1_level>;

		vdd_mmsscc_mx-supply = <&pmcobalt_s9_level>;

		clock-names = "xo", "gpll0", "gpll0_div",

				"pclk0_src", "pclk1_src",

				"byte0_src", "byte1_src",

drivers/clk/msm/clock-mmss-cobalt.c

+17 −12
Original line number Diff line number Diff line
@@ -83,6 +83,7 @@ DEFINE_EXT_CLK(ext_dp_phy_pll_vco, NULL); 
DEFINE_EXT_CLK(ext_dp_phy_pll_link, NULL);



static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);

static DEFINE_VDD_REGULATORS(vdd_mmsscc_mx, VDD_DIG_NUM, 1, vdd_corner, NULL);



static struct alpha_pll_masks pll_masks_p = {

	.lock_mask = BIT(31),
@@ -102,7 +103,7 @@ static struct pll_vote_clk mmpll0_pll = { 
		.parent = &mmsscc_xo.c,

		.dbg_name = "mmpll0",

		.ops = &clk_ops_pll_vote,

		VDD_DIG_FMAX_MAP2(LOWER, 404000000, NOMINAL, 808000000),

		VDD_MM_PLL_FMAX_MAP2(LOWER, 404000000, NOMINAL, 808000000),

		CLK_INIT(mmpll0_pll.c),

	},

};
@@ -119,7 +120,7 @@ static struct pll_vote_clk mmpll1_pll = { 
		.parent = &mmsscc_xo.c,

		.dbg_name = "mmpll1_pll",

		.ops = &clk_ops_pll_vote,

		VDD_DIG_FMAX_MAP2(LOWER, 406000000, NOMINAL, 812000000),

		VDD_MM_PLL_FMAX_MAP2(LOWER, 406000000, NOMINAL, 812000000),

		CLK_INIT(mmpll1_pll.c),

	},

};
@@ -136,7 +137,7 @@ static struct alpha_pll_clk mmpll3_pll = { 
		.parent = &mmsscc_xo.c,

		.dbg_name = "mmpll3_pll",

		.ops = &clk_ops_fixed_fabia_alpha_pll,

		VDD_DIG_FMAX_MAP2(LOWER, 465000000, LOW, 930000000),

		VDD_MM_PLL_FMAX_MAP2(LOWER, 465000000, LOW, 930000000),

		CLK_INIT(mmpll3_pll.c),

	},

};
@@ -153,7 +154,7 @@ static struct alpha_pll_clk mmpll4_pll = { 
		.parent = &mmsscc_xo.c,

		.dbg_name = "mmpll4_pll",

		.ops = &clk_ops_fixed_fabia_alpha_pll,

		VDD_DIG_FMAX_MAP2(LOWER, 384000000, LOW, 768000000),

		VDD_MM_PLL_FMAX_MAP2(LOWER, 384000000, LOW, 768000000),

		CLK_INIT(mmpll4_pll.c),

	},

};
@@ -170,7 +171,7 @@ static struct alpha_pll_clk mmpll5_pll = { 
		.parent = &mmsscc_xo.c,

		.dbg_name = "mmpll5_pll",

		.ops = &clk_ops_fixed_fabia_alpha_pll,

		VDD_DIG_FMAX_MAP2(LOWER, 412500000, LOW, 825000000),

		VDD_MM_PLL_FMAX_MAP2(LOWER, 412500000, LOW, 825000000),

		CLK_INIT(mmpll5_pll.c),

	},

};
@@ -187,7 +188,7 @@ static struct alpha_pll_clk mmpll6_pll = { 
		.parent = &mmsscc_xo.c,

		.dbg_name = "mmpll6_pll",

		.ops = &clk_ops_fixed_fabia_alpha_pll,

		VDD_DIG_FMAX_MAP2(LOWER, 360000000, NOMINAL, 720000000),

		VDD_MM_PLL_FMAX_MAP2(LOWER, 360000000, NOMINAL, 720000000),

		CLK_INIT(mmpll6_pll.c),

	},

};
@@ -204,7 +205,7 @@ static struct alpha_pll_clk mmpll7_pll = { 
		.parent = &mmsscc_xo.c,

		.dbg_name = "mmpll7_pll",

		.ops = &clk_ops_fixed_fabia_alpha_pll,

		VDD_DIG_FMAX_MAP2(LOWER, 480000000, NOMINAL, 960000000),

		VDD_MM_PLL_FMAX_MAP1(LOW, 960000000),

		CLK_INIT(mmpll7_pll.c),

	},

};
@@ -221,7 +222,7 @@ static struct alpha_pll_clk mmpll10_pll = { 
		.parent = &mmsscc_xo.c,

		.dbg_name = "mmpll10_pll",

		.ops = &clk_ops_fixed_fabia_alpha_pll,

		VDD_DIG_FMAX_MAP2(LOWER, 288000000, NOMINAL, 576000000),

		VDD_MM_PLL_FMAX_MAP2(LOWER, 288000000, NOMINAL, 576000000),

		CLK_INIT(mmpll10_pll.c),

	},

};
@@ -2745,10 +2746,6 @@ static void msm_mmsscc_v2_fixup(void) 
	csiphy_clk_src.c.fmax[VDD_DIG_LOW] = 256000000;



	dp_pixel_clk_src.c.fmax[VDD_DIG_LOWER] = 148380000;



	video_subcore0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000;

	video_subcore1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000;

	video_core_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000;

}



int msm_mmsscc_cobalt_probe(struct platform_device *pdev)
@@ -2783,6 +2780,14 @@ int msm_mmsscc_cobalt_probe(struct platform_device *pdev) 
		return PTR_ERR(reg);

	}



	reg = vdd_mmsscc_mx.regulator[0] = devm_regulator_get(&pdev->dev,

							"vdd_mmsscc_mx");

	if (IS_ERR(reg)) {

		if (PTR_ERR(reg) != -EPROBE_DEFER)

			dev_err(&pdev->dev, "Unable to get vdd_mmsscc_mx regulator!");

		return PTR_ERR(reg);

	}



	tmp = mmsscc_xo.c.parent = devm_clk_get(&pdev->dev, "xo");

	if (IS_ERR(tmp)) {

		if (PTR_ERR(tmp) != -EPROBE_DEFER)

drivers/clk/msm/vdd-level-cobalt.h

+18 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
		[VDD_DIG_##l1] = (f1),		\

	},					\

	.num_fmax = VDD_DIG_NUM



#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \

	.vdd_class = &vdd_dig,			\

	.fmax = (unsigned long[VDD_DIG_NUM]) {	\
@@ -40,6 +41,7 @@ 
		[VDD_DIG_##l3] = (f3),		\

	},					\

	.num_fmax = VDD_DIG_NUM



#define VDD_DIG_FMAX_MAP4(l1, f1, l2, f2, l3, f3, l4, f4) \

	.vdd_class = &vdd_dig,			\

	.fmax = (unsigned long[VDD_DIG_NUM]) {	\
@@ -66,6 +68,22 @@ 
	},					\

	.num_fmax = VDD_DIG_NUM



#define VDD_MM_PLL_FMAX_MAP1(l1, f1) \

	.vdd_class = &vdd_mmsscc_mx,		\

	.fmax = (unsigned long[VDD_DIG_NUM]) {	\

		[VDD_DIG_##l1] = (f1),		\

	},					\

	.num_fmax = VDD_DIG_NUM



#define VDD_MM_PLL_FMAX_MAP2(l1, f1, l2, f2) \

	.vdd_class = &vdd_mmsscc_mx,		\

	.fmax = (unsigned long[VDD_DIG_NUM]) {	\

		[VDD_DIG_##l1] = (f1),		\

		[VDD_DIG_##l2] = (f2),		\

	},					\

	.num_fmax = VDD_DIG_NUM





#define VDD_GPU_PLL_FMAX_MAP1(l1, f1)  \

	.vdd_class = &vdd_gpucc_mx,		\

	.fmax = (unsigned long[VDD_DIG_NUM]) {	\