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Commit d86e9af6 authored by Andrew Lunn's avatar Andrew Lunn Committed by Jason Cooper
Browse files

irqchip: orion: Fix getting generic chip pointer. 



Enabling SPARSE_IRQ shows up a bug in the irq-orion bridge interrupt
handler. The bridge interrupt is implemented using a single generic
chip. Thus the parameter passed to irq_get_domain_generic_chip()
should always be zero.

Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Acked-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Fixes: 9dbd90f1 ("irqchip: Add support for Marvell Orion SoCs")
Cc: <stable@vger.kernel.org> # v3.11+
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent e0318ec3

drivers/irqchip/irq-orion.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -111,7 +111,8 @@ IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_irq_init); 
static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc)

static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc)

{

{

	struct irq_domain *d = irq_get_handler_data(irq);

	struct irq_domain *d = irq_get_handler_data(irq);

	struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, irq);



	struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);

	u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) &

	u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) &

		   gc->mask_cache;

		   gc->mask_cache;