Loading drivers/platform/msm/ipa/ipa_v3/ipa.c +4 −35 Original line number Diff line number Diff line Loading @@ -2248,7 +2248,6 @@ static int ipa3_q6_set_ex_path_to_apps(void) struct ipahal_imm_cmd_register_write reg_write; struct ipahal_imm_cmd_pyld *cmd_pyld; int retval; struct ipahal_reg_valmask valmask; desc = kcalloc(ipa3_ctx->ipa_num_pipes, sizeof(struct ipa3_desc), GFP_KERNEL); Loading @@ -2263,40 +2262,10 @@ static int ipa3_q6_set_ex_path_to_apps(void) if (ep_idx == -1) continue; if (ipa3_ctx->ep[ep_idx].valid && ipa3_ctx->ep[ep_idx].skip_ep_cfg) { BUG_ON(num_descs >= ipa3_ctx->ipa_num_pipes); reg_write.skip_pipeline_clear = false; reg_write.pipeline_clear_options = IPAHAL_HPS_CLEAR; reg_write.offset = ipahal_get_reg_n_ofst(IPA_ENDP_STATUS_n, ep_idx); ipahal_get_status_ep_valmask( ipa3_get_ep_mapping(IPA_CLIENT_APPS_LAN_CONS), &valmask); reg_write.value = valmask.val; reg_write.value_mask = valmask.mask; cmd_pyld = ipahal_construct_imm_cmd( IPA_IMM_CMD_REGISTER_WRITE, ®_write, false); if (!cmd_pyld) { IPAERR("fail construct register_write cmd\n"); BUG(); } desc[num_descs].opcode = ipahal_imm_cmd_get_opcode( IPA_IMM_CMD_REGISTER_WRITE); desc[num_descs].type = IPA_IMM_CMD_DESC; desc[num_descs].callback = ipa3_destroy_imm; desc[num_descs].user1 = cmd_pyld; desc[num_descs].pyld = cmd_pyld->data; desc[num_descs].len = cmd_pyld->len; num_descs++; } /* disable statuses for modem producers */ if (IPA_CLIENT_IS_Q6_PROD(client_idx)) { /* disable statuses for all modem controlled prod pipes */ if (IPA_CLIENT_IS_Q6_PROD(client_idx) || (ipa3_ctx->ep[ep_idx].valid && ipa3_ctx->ep[ep_idx].skip_ep_cfg)) { ipa_assert_on(num_descs >= ipa3_ctx->ipa_num_pipes); reg_write.skip_pipeline_clear = false; Loading drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c +0 −17 Original line number Diff line number Diff line Loading @@ -1612,20 +1612,3 @@ void ipahal_get_fltrt_hash_flush_valmask( valmask->mask = valmask->val; } void ipahal_get_status_ep_valmask(int pipe_num, struct ipahal_reg_valmask *valmask) { if (!valmask) { IPAHAL_ERR("Input error\n"); return; } valmask->val = (pipe_num & IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK) << IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT; valmask->mask = IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK << IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT; } drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h +0 −2 Original line number Diff line number Diff line Loading @@ -467,8 +467,6 @@ void ipahal_get_aggr_force_close_valmask(int ep_idx, void ipahal_get_fltrt_hash_flush_valmask( struct ipahal_reg_fltrt_hash_flush *flush, struct ipahal_reg_valmask *valmask); void ipahal_get_status_ep_valmask(int pipe_num, struct ipahal_reg_valmask *valmask); #endif /* _IPAHAL_REG_H_ */ Loading
drivers/platform/msm/ipa/ipa_v3/ipa.c +4 −35 Original line number Diff line number Diff line Loading @@ -2248,7 +2248,6 @@ static int ipa3_q6_set_ex_path_to_apps(void) struct ipahal_imm_cmd_register_write reg_write; struct ipahal_imm_cmd_pyld *cmd_pyld; int retval; struct ipahal_reg_valmask valmask; desc = kcalloc(ipa3_ctx->ipa_num_pipes, sizeof(struct ipa3_desc), GFP_KERNEL); Loading @@ -2263,40 +2262,10 @@ static int ipa3_q6_set_ex_path_to_apps(void) if (ep_idx == -1) continue; if (ipa3_ctx->ep[ep_idx].valid && ipa3_ctx->ep[ep_idx].skip_ep_cfg) { BUG_ON(num_descs >= ipa3_ctx->ipa_num_pipes); reg_write.skip_pipeline_clear = false; reg_write.pipeline_clear_options = IPAHAL_HPS_CLEAR; reg_write.offset = ipahal_get_reg_n_ofst(IPA_ENDP_STATUS_n, ep_idx); ipahal_get_status_ep_valmask( ipa3_get_ep_mapping(IPA_CLIENT_APPS_LAN_CONS), &valmask); reg_write.value = valmask.val; reg_write.value_mask = valmask.mask; cmd_pyld = ipahal_construct_imm_cmd( IPA_IMM_CMD_REGISTER_WRITE, ®_write, false); if (!cmd_pyld) { IPAERR("fail construct register_write cmd\n"); BUG(); } desc[num_descs].opcode = ipahal_imm_cmd_get_opcode( IPA_IMM_CMD_REGISTER_WRITE); desc[num_descs].type = IPA_IMM_CMD_DESC; desc[num_descs].callback = ipa3_destroy_imm; desc[num_descs].user1 = cmd_pyld; desc[num_descs].pyld = cmd_pyld->data; desc[num_descs].len = cmd_pyld->len; num_descs++; } /* disable statuses for modem producers */ if (IPA_CLIENT_IS_Q6_PROD(client_idx)) { /* disable statuses for all modem controlled prod pipes */ if (IPA_CLIENT_IS_Q6_PROD(client_idx) || (ipa3_ctx->ep[ep_idx].valid && ipa3_ctx->ep[ep_idx].skip_ep_cfg)) { ipa_assert_on(num_descs >= ipa3_ctx->ipa_num_pipes); reg_write.skip_pipeline_clear = false; Loading
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c +0 −17 Original line number Diff line number Diff line Loading @@ -1612,20 +1612,3 @@ void ipahal_get_fltrt_hash_flush_valmask( valmask->mask = valmask->val; } void ipahal_get_status_ep_valmask(int pipe_num, struct ipahal_reg_valmask *valmask) { if (!valmask) { IPAHAL_ERR("Input error\n"); return; } valmask->val = (pipe_num & IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK) << IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT; valmask->mask = IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK << IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT; }
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h +0 −2 Original line number Diff line number Diff line Loading @@ -467,8 +467,6 @@ void ipahal_get_aggr_force_close_valmask(int ep_idx, void ipahal_get_fltrt_hash_flush_valmask( struct ipahal_reg_fltrt_hash_flush *flush, struct ipahal_reg_valmask *valmask); void ipahal_get_status_ep_valmask(int pipe_num, struct ipahal_reg_valmask *valmask); #endif /* _IPAHAL_REG_H_ */