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Commit d4b34c6c authored by Seungwhan Youn's avatar Seungwhan Youn Committed by Kukjin Kim
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ARM: S5P: Reduce duplicated EPLL control codes 



S5P Samsung SoCs has a EPLL to support various PLL clock sources for other
H/W blocks. Until now, to control EPLL, each of SoCs make their own functions
in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and
'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move
these duplicated codes to common EPLL functions that use platform wide.

Signed-off-by: default avatarSeungwhan Youn <sw.youn@samsung.com>
Acked-by: default avatarJassi Brar <jassi.brar@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 900fa019

arch/arm/mach-s5p64x0/clock-s5p6440.c

+2 −2
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate) 
}



static struct clk_ops s5p6440_epll_ops = {

	.get_rate = s5p64x0_epll_get_rate,

	.get_rate = s5p_epll_get_rate,

	.set_rate = s5p6440_epll_set_rate,

};
@@ -548,7 +548,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) 


	/* Set S5P6440 functions for clk_fout_epll */



	clk_fout_epll.enable = s5p64x0_epll_enable;

	clk_fout_epll.enable = s5p_epll_enable;

	clk_fout_epll.ops = &s5p6440_epll_ops;



	clk_48m.enable = s5p64x0_clk48m_ctrl;

arch/arm/mach-s5p64x0/clock-s5p6450.c

+2 −2
Original line number Diff line number Diff line
@@ -86,7 +86,7 @@ static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate) 
}



static struct clk_ops s5p6450_epll_ops = {

	.get_rate = s5p64x0_epll_get_rate,

	.get_rate = s5p_epll_get_rate,

	.set_rate = s5p6450_epll_set_rate,

};
@@ -581,7 +581,7 @@ void __init_or_cpufreq s5p6450_setup_clocks(void) 


	/* Set S5P6450 functions for clk_fout_epll */



	clk_fout_epll.enable = s5p64x0_epll_enable;

	clk_fout_epll.enable = s5p_epll_enable;

	clk_fout_epll.ops = &s5p6450_epll_ops;



	clk_48m.enable = s5p64x0_clk48m_ctrl;

arch/arm/mach-s5p64x0/clock.c

+0 −18
Original line number Diff line number Diff line
@@ -73,24 +73,6 @@ static const u32 clock_table[][3] = { 
	{L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},

};



int s5p64x0_epll_enable(struct clk *clk, int enable)

{

	unsigned int ctrlbit = clk->ctrlbit;

	unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;



	if (enable)

		__raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);

	else

		__raw_writel(epll_con, S5P64X0_EPLL_CON);



	return 0;

}



unsigned long s5p64x0_epll_get_rate(struct clk *clk)

{

	return clk->rate;

}



unsigned long s5p64x0_armclk_get_rate(struct clk *clk)

{

	unsigned long rate = clk_get_rate(clk->parent);

arch/arm/mach-s5p64x0/include/mach/regs-clock.h

+2 −0
Original line number Diff line number Diff line
@@ -60,4 +60,6 @@ 
#define ARM_DIV_RATIO_SHIFT		0

#define ARM_DIV_MASK			(0xF << ARM_DIV_RATIO_SHIFT)



#define S5P_EPLL_CON			S5P64X0_EPLL_CON



#endif /* __ASM_ARCH_REGS_CLOCK_H */

arch/arm/mach-s5pc100/clock.c

+2 −20
Original line number Diff line number Diff line
@@ -273,24 +273,6 @@ static struct clksrc_clk clk_div_hdmi = { 
	.reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },

};



static int s5pc100_epll_enable(struct clk *clk, int enable)

{

	unsigned int ctrlbit = clk->ctrlbit;

	unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;



	if (enable)

		__raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);

	else

		__raw_writel(epll_con, S5P_EPLL_CON);



	return 0;

}



static unsigned long s5pc100_epll_get_rate(struct clk *clk)

{

	return clk->rate;

}



static u32 epll_div[][4] = {

	{ 32750000,	131, 3, 4 },

	{ 32768000,	131, 3, 4 },
@@ -347,7 +329,7 @@ static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate) 
}



static struct clk_ops s5pc100_epll_ops = {

	.get_rate = s5pc100_epll_get_rate,

	.get_rate = s5p_epll_get_rate,

	.set_rate = s5pc100_epll_set_rate,

};
@@ -1261,7 +1243,7 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) 
	unsigned int ptr;



	/* Set S5PC100 functions for clk_fout_epll */

	clk_fout_epll.enable = s5pc100_epll_enable;

	clk_fout_epll.enable = s5p_epll_enable;

	clk_fout_epll.ops = &s5pc100_epll_ops;



	printk(KERN_DEBUG "%s: registering clocks\n", __func__);