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Commit d464207c authored by Eric W. Biederman's avatar Eric W. Biederman Committed by H. Peter Anvin
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x86, ioapic: Optimize pin_2_irq 



Now that all ioapics have valid gsi_base values use this to
accellerate pin_2_irq.  In the case of acpi this also ensures
that pin_2_irq will compute the same irq value for an ioapic
pin as acpi will.

Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
LKML-Reference: <1269936436-7039-12-git-send-email-ebiederm@xmission.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent 7716a5c4

arch/x86/kernel/apic/io_apic.c

+4 −9
Original line number Original line Diff line number Diff line
@@ -1019,7 +1019,7 @@ static inline int irq_trigger(int idx) 
int (*ioapic_renumber_irq)(int ioapic, int irq);

int (*ioapic_renumber_irq)(int ioapic, int irq);

static int pin_2_irq(int idx, int apic, int pin)

static int pin_2_irq(int idx, int apic, int pin)

{

{

	int irq, i;

	int irq;

	int bus = mp_irqs[idx].srcbus;

	int bus = mp_irqs[idx].srcbus;





	/*

	/*
@@ -1031,18 +1031,13 @@ static int pin_2_irq(int idx, int apic, int pin) 
	if (test_bit(bus, mp_bus_not_pci)) {

	if (test_bit(bus, mp_bus_not_pci)) {

		irq = mp_irqs[idx].srcbusirq;

		irq = mp_irqs[idx].srcbusirq;

	} else {

	} else {

		/*

		u32 gsi = mp_gsi_routing[apic].gsi_base + pin;

		 * PCI IRQs are mapped in order

		 */

		i = irq = 0;

		while (i < apic)

			irq += nr_ioapic_registers[i++];

		irq += pin;

		/*

		/*

                 * For MPS mode, so far only needed by ES7000 platform

                 * For MPS mode, so far only needed by ES7000 platform

                 */

                 */

		if (ioapic_renumber_irq)

		if (ioapic_renumber_irq)

			irq = ioapic_renumber_irq(apic, irq);

			gsi = ioapic_renumber_irq(apic, gsi);

		irq = gsi;

	}

	}





#ifdef CONFIG_X86_32

#ifdef CONFIG_X86_32