Merge "clock: qcom: Update the list of clocks supported on MSMFalcon" (d43110ab) · Commits · e / devices / android_kernel_sony_msm8998

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+10 −0

Original line number	Diff line number	Diff line
		@@ -314,6 +314,16 @@
		#clock-cells = <1>;
		};

		clock_mmss: qcom,dummycc {
		compatible = "qcom,dummycc";
		#clock-cells = <1>;
		};

		clock_gfx: qcom,dummycc {
		compatible = "qcom,dummycc";
		#clock-cells = <1>;
		};

		qcom,ipc-spinlock@1f40000 {
		compatible = "qcom,ipc-spinlock-sfpb";
		reg = <0x1f40000 0x8000>;

include/dt-bindings/clock/qcom,gcc-msmfalcon.h

+222 −223

Original line number	Diff line number	Diff line
		@@ -14,230 +14,229 @@
		#ifndef _DT_BINDINGS_CLK_MSM_GCC_FALCON_H
		#define _DT_BINDINGS_CLK_MSM_GCC_FALCON_H

		/* Clocks */
		#define GPLL0 0
		#define GPLL1 1
		#define GPLL2 2
		#define GPLL3 3
		#define GPLL4 4
		#define GPLL5 5
		#define GPLL6 6
		#define MMSS_QM_CORE_CLK_SRC 7
		#define USB30_MASTER_CLK_SRC 8
		#define USB30_MOCK_UTMI_CLK_SRC 9
		#define USB3_PHY_AUX_CLK_SRC 10
		#define USB20_MASTER_CLK_SRC 11
		#define USB20_MOCK_UTMI_CLK_SRC 12
		#define SDCC2_APPS_CLK_SRC 13
		#define SDCC1_ICE_CORE_CLK_SRC 14
		#define SDCC1_APPS_CLK_SRC 15
		#define BLSP1_QUP1_SPI_APPS_CLK_SRC 16
		#define BLSP1_QUP1_I2C_APPS_CLK_SRC 17
		#define BLSP1_UART1_APPS_CLK_SRC 18
		#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
		#define BLSP1_QUP2_I2C_APPS_CLK_SRC 20
		#define BLSP1_UART2_APPS_CLK_SRC 21
		#define BLSP1_QUP3_SPI_APPS_CLK_SRC 22
		#define BLSP1_QUP3_I2C_APPS_CLK_SRC 23
		#define BLSP1_QUP4_SPI_APPS_CLK_SRC 24
		#define BLSP1_QUP4_I2C_APPS_CLK_SRC 25
		#define BLSP2_QUP1_SPI_APPS_CLK_SRC 26
		#define BLSP2_QUP1_I2C_APPS_CLK_SRC 27
		#define BLSP2_UART1_APPS_CLK_SRC 28
		#define BLSP2_QUP2_SPI_APPS_CLK_SRC 29
		#define BLSP2_QUP2_I2C_APPS_CLK_SRC 30
		#define BLSP2_UART2_APPS_CLK_SRC 31
		#define BLSP2_QUP3_SPI_APPS_CLK_SRC 32
		#define BLSP2_QUP3_I2C_APPS_CLK_SRC 33
		#define BLSP2_QUP4_SPI_APPS_CLK_SRC 34
		#define BLSP2_QUP4_I2C_APPS_CLK_SRC 35
		#define PDM2_CLK_SRC 36
		#define HMSS_AHB_CLK_SRC 37
		#define BIMC_HMSS_AXI_CLK_SRC 38
		#define HMSS_RBCPR_CLK_SRC 39
		#define HMSS_GPLL0_CLK_SRC 40
		#define HMSS_GPLL4_CLK_SRC 41
		#define GP1_CLK_SRC 42
		#define GP2_CLK_SRC 43
		#define GP3_CLK_SRC 44
		#define UFS_AXI_CLK_SRC 45
		#define UFS_ICE_CORE_CLK_SRC 46
		#define UFS_UNIPRO_CORE_CLK_SRC 47
		#define UFS_PHY_AUX_CLK_SRC 48
		#define QSPI_SER_CLK_SRC 49
		#define GLM_CLK_SRC 50
		#define GCC_MMSS_SYS_NOC_AXI_CLK 51
		#define GCC_MMSS_NOC_CFG_AHB_CLK 52
		#define GCC_MMSS_QM_CORE_CLK 53
		#define GCC_MMSS_QM_AHB_CLK 54
		#define GCC_USB30_MASTER_CLK 55
		#define GCC_USB30_SLEEP_CLK 56
		#define GCC_USB30_MOCK_UTMI_CLK 57
		#define GCC_USB3_PHY_AUX_CLK 58
		#define GCC_USB3_PHY_PIPE_CLK 59
		#define GCC_USB20_MASTER_CLK 60
		#define GCC_USB20_SLEEP_CLK 61
		#define GCC_USB20_MOCK_UTMI_CLK 62
		#define GCC_USB_PHY_CFG_AHB2PHY_CLK 63
		#define GCC_SDCC2_APPS_CLK 64
		#define GCC_SDCC2_AHB_CLK 65
		#define GCC_SDCC1_APPS_CLK 66
		#define GCC_SDCC1_AHB_CLK 67
		#define GCC_SDCC1_ICE_CORE_CLK 68
		#define GCC_BLSP1_AHB_CLK 69
		#define GCC_BLSP1_SLEEP_CLK 70
		#define GCC_BLSP1_QUP1_SPI_APPS_CLK 71
		#define GCC_BLSP1_QUP1_I2C_APPS_CLK 72
		#define GCC_BLSP1_UART1_APPS_CLK 73
		#define GCC_BLSP1_QUP2_SPI_APPS_CLK 74
		#define GCC_BLSP1_QUP2_I2C_APPS_CLK 75
		#define GCC_BLSP1_UART2_APPS_CLK 76
		#define GCC_BLSP1_QUP3_SPI_APPS_CLK 77
		#define GCC_BLSP1_QUP3_I2C_APPS_CLK 78
		#define GCC_BLSP1_QUP4_SPI_APPS_CLK 79
		#define GCC_BLSP1_QUP4_I2C_APPS_CLK 80
		#define GCC_BLSP2_AHB_CLK 81
		#define GCC_BLSP2_SLEEP_CLK 82
		#define GCC_BLSP2_QUP1_SPI_APPS_CLK 83
		#define GCC_BLSP2_QUP1_I2C_APPS_CLK 84
		#define GCC_BLSP2_UART1_APPS_CLK 85
		#define GCC_BLSP2_QUP2_SPI_APPS_CLK 86
		#define GCC_BLSP2_QUP2_I2C_APPS_CLK 87
		#define GCC_BLSP2_UART2_APPS_CLK 88
		#define GCC_BLSP2_QUP3_SPI_APPS_CLK 89
		#define GCC_BLSP2_QUP3_I2C_APPS_CLK 90
		#define GCC_BLSP2_QUP4_SPI_APPS_CLK 91
		#define GCC_BLSP2_QUP4_I2C_APPS_CLK 92
		#define GCC_PDM_AHB_CLK 93
		#define GCC_PDM_XO4_CLK 94
		#define GCC_PDM2_CLK 95
		#define GCC_PRNG_AHB_CLK 96
		#define GCC_BIMC_GFX_CLK 97
		#define GCC_MCCC_CFG_AHB_CLK 98
		#define GCC_LPASS_TRIG_CLK 99
		#define GCC_LPASS_AT_CLK 100
		#define GCC_TURING_TRIG_CLK 101
		#define GCC_TURING_AT_CLK 102
		#define GCC_HMSS_AHB_CLK 103
		#define GCC_BIMC_HMSS_AXI_CLK 104
		#define GCC_HMSS_RBCPR_CLK 105
		#define GCC_HMSS_TRIG_CLK 106
		#define GCC_HMSS_AT_CLK 107
		#define GCC_HMSS_DVM_BUS_CLK 108
		#define GCC_GP1_CLK 109
		#define GCC_GP2_CLK 110
		#define GCC_GP3_CLK 111
		#define GCC_UFS_AXI_CLK 112
		#define GCC_UFS_AHB_CLK 113
		#define GCC_UFS_TX_SYMBOL_0_CLK 114
		#define GCC_UFS_RX_SYMBOL_0_CLK 115
		#define GCC_UFS_UNIPRO_CORE_CLK 116
		#define GCC_UFS_ICE_CORE_CLK 117
		#define GCC_UFS_PHY_AUX_CLK 118
		#define GCC_UFS_RX_SYMBOL_1_CLK 119
		#define GCC_AGGRE2_USB3_AXI_CLK 120
		#define GCC_AGGRE2_UFS_AXI_CLK 121
		#define GCC_QSPI_AHB_CLK 122
		#define GCC_QSPI_SER_CLK 123
		#define GCC_GLM_AHB_CLK 124
		#define GCC_GLM_CLK 125
		#define GCC_GLM_XO_CLK 126
		#define GCC_WCSS_AHB_S0_CLK 127
		#define GCC_WCSS_AXI_M_CLK 128
		#define GCC_WCSS_ECAHB_CLK 129
		#define GCC_WCSS_SHDREG_AHB_CLK 130
		#define GCC_GPU_CFG_AHB_CLK 131
		#define GCC_GPU_BIMC_GFX_SRC_CLK 132
		#define GCC_GPU_BIMC_GFX_CLK 133
		#define GCC_GPU_SNOC_DVM_GFX_CLK 134
		#define BIMC_HMSS_AXI_CLK_SRC 0
		#define BLSP1_QUP1_I2C_APPS_CLK_SRC 1
		#define BLSP1_QUP1_SPI_APPS_CLK_SRC 2
		#define BLSP1_QUP2_I2C_APPS_CLK_SRC 3
		#define BLSP1_QUP2_SPI_APPS_CLK_SRC 4
		#define BLSP1_QUP3_I2C_APPS_CLK_SRC 5
		#define BLSP1_QUP3_SPI_APPS_CLK_SRC 6
		#define BLSP1_QUP4_I2C_APPS_CLK_SRC 7
		#define BLSP1_QUP4_SPI_APPS_CLK_SRC 8
		#define BLSP1_UART1_APPS_CLK_SRC 9
		#define BLSP1_UART2_APPS_CLK_SRC 10
		#define BLSP2_QUP1_I2C_APPS_CLK_SRC 11
		#define BLSP2_QUP1_SPI_APPS_CLK_SRC 12
		#define BLSP2_QUP2_I2C_APPS_CLK_SRC 13
		#define BLSP2_QUP2_SPI_APPS_CLK_SRC 14
		#define BLSP2_QUP3_I2C_APPS_CLK_SRC 15
		#define BLSP2_QUP3_SPI_APPS_CLK_SRC 16
		#define BLSP2_QUP4_I2C_APPS_CLK_SRC 17
		#define BLSP2_QUP4_SPI_APPS_CLK_SRC 18
		#define BLSP2_UART1_APPS_CLK_SRC 19
		#define BLSP2_UART2_APPS_CLK_SRC 20
		#define GCC_AGGRE2_UFS_AXI_CLK 21
		#define GCC_AGGRE2_USB3_AXI_CLK 22
		#define GCC_BIMC_GFX_CLK 23
		#define GCC_BIMC_HMSS_AXI_CLK 24
		#define GCC_BIMC_MSS_Q6_AXI_CLK 25
		#define GCC_BLSP1_AHB_CLK 26
		#define GCC_BLSP1_QUP1_I2C_APPS_CLK 27
		#define GCC_BLSP1_QUP1_SPI_APPS_CLK 28
		#define GCC_BLSP1_QUP2_I2C_APPS_CLK 29
		#define GCC_BLSP1_QUP2_SPI_APPS_CLK 30
		#define GCC_BLSP1_QUP3_I2C_APPS_CLK 31
		#define GCC_BLSP1_QUP3_SPI_APPS_CLK 32
		#define GCC_BLSP1_QUP4_I2C_APPS_CLK 33
		#define GCC_BLSP1_QUP4_SPI_APPS_CLK 34
		#define GCC_BLSP1_UART1_APPS_CLK 35
		#define GCC_BLSP1_UART2_APPS_CLK 36
		#define GCC_BLSP2_AHB_CLK 37
		#define GCC_BLSP2_QUP1_I2C_APPS_CLK 38
		#define GCC_BLSP2_QUP1_SPI_APPS_CLK 39
		#define GCC_BLSP2_QUP2_I2C_APPS_CLK 40
		#define GCC_BLSP2_QUP2_SPI_APPS_CLK 41
		#define GCC_BLSP2_QUP3_I2C_APPS_CLK 42
		#define GCC_BLSP2_QUP3_SPI_APPS_CLK 43
		#define GCC_BLSP2_QUP4_I2C_APPS_CLK 44
		#define GCC_BLSP2_QUP4_SPI_APPS_CLK 45
		#define GCC_BLSP2_UART1_APPS_CLK 46
		#define GCC_BLSP2_UART2_APPS_CLK 47
		#define GCC_BOOT_ROM_AHB_CLK 48
		#define GCC_CFG_NOC_USB2_AXI_CLK 49
		#define GCC_CFG_NOC_USB3_AXI_CLK 50
		#define GCC_GLM_AHB_CLK 51
		#define GCC_GLM_CLK 52
		#define GCC_GP1_CLK 53
		#define GCC_GP2_CLK 54
		#define GCC_GP3_CLK 55
		#define GCC_GPU_BIMC_GFX_CLK 56
		#define GCC_GPU_BIMC_GFX_SRC_CLK 57
		#define GCC_GPU_CFG_AHB_CLK 58
		#define GCC_GPU_SNOC_DVM_GFX_CLK 59
		#define GCC_HMSS_AHB_CLK 60
		#define GCC_HMSS_DVM_BUS_CLK 61
		#define GCC_HMSS_RBCPR_CLK 62
		#define GCC_MMSS_NOC_CFG_AHB_CLK 63
		#define GCC_MMSS_QM_AHB_CLK 64
		#define GCC_MMSS_QM_CORE_CLK 65
		#define GCC_MMSS_SYS_NOC_AXI_CLK 66
		#define GCC_PDM2_CLK 67
		#define GCC_PDM_AHB_CLK 68
		#define GCC_PRNG_AHB_CLK 69
		#define GCC_QSPI_AHB_CLK 70
		#define GCC_QSPI_SER_CLK 71
		#define GCC_SDCC1_AHB_CLK 72
		#define GCC_SDCC1_APPS_CLK 73
		#define GCC_SDCC1_ICE_CORE_CLK 74
		#define GCC_SDCC2_AHB_CLK 75
		#define GCC_SDCC2_APPS_CLK 76
		#define GCC_UFS_AHB_CLK 77
		#define GCC_UFS_AXI_CLK 78
		#define GCC_UFS_ICE_CORE_CLK 79
		#define GCC_UFS_PHY_AUX_CLK 80
		#define GCC_UFS_RX_SYMBOL_0_CLK 81
		#define GCC_UFS_RX_SYMBOL_1_CLK 82
		#define GCC_UFS_TX_SYMBOL_0_CLK 83
		#define GCC_UFS_UNIPRO_CORE_CLK 84
		#define GCC_USB20_MASTER_CLK 85
		#define GCC_USB20_MOCK_UTMI_CLK 86
		#define GCC_USB20_SLEEP_CLK 87
		#define GCC_USB30_MASTER_CLK 88
		#define GCC_USB30_MOCK_UTMI_CLK 89
		#define GCC_USB30_SLEEP_CLK 90
		#define GCC_USB3_PHY_AUX_CLK 91
		#define GCC_USB3_PHY_PIPE_CLK 92
		#define GCC_USB_PHY_CFG_AHB2PHY_CLK 93
		#define GCC_WCSS_AHB_S0_CLK 94
		#define GCC_WCSS_AXI_M_CLK 95
		#define GCC_WCSS_ECAHB_CLK 96
		#define GCC_WCSS_SHDREG_AHB_CLK 97
		#define GLM_CLK_SRC 98
		#define GP1_CLK_SRC 99
		#define GP2_CLK_SRC 100
		#define GP3_CLK_SRC 101
		#define GPLL0 102
		#define GPLL0_OUT_AUX 103
		#define GPLL0_OUT_AUX2 104
		#define GPLL0_OUT_EARLY 105
		#define GPLL0_OUT_MAIN 106
		#define GPLL0_OUT_TEST 107
		#define GPLL1 108
		#define GPLL1_OUT_AUX 109
		#define GPLL1_OUT_AUX2 110
		#define GPLL1_OUT_EARLY 111
		#define GPLL1_OUT_MAIN 112
		#define GPLL1_OUT_TEST 113
		#define GPLL2 114
		#define GPLL2_OUT_AUX 115
		#define GPLL2_OUT_AUX2 116
		#define GPLL2_OUT_EARLY 117
		#define GPLL2_OUT_MAIN 118
		#define GPLL2_OUT_TEST 119
		#define GPLL3 120
		#define GPLL3_OUT_AUX 121
		#define GPLL3_OUT_AUX2 122
		#define GPLL3_OUT_EARLY 123
		#define GPLL3_OUT_MAIN 124
		#define GPLL3_OUT_TEST 125
		#define GPLL4 126
		#define GPLL4_OUT_AUX 127
		#define GPLL4_OUT_AUX2 128
		#define GPLL4_OUT_EARLY 129
		#define GPLL4_OUT_MAIN 130
		#define GPLL4_OUT_TEST 131
		#define GPLL5 132
		#define GPLL5_OUT_AUX 133
		#define GPLL5_OUT_AUX2 134
		#define GPLL5_OUT_EARLY 135
		#define GPLL5_OUT_MAIN 136
		#define GPLL5_OUT_TEST 137
		#define GPLL6 138
		#define GPLL6_OUT_AUX 139
		#define GPLL6_OUT_AUX2 140
		#define GPLL6_OUT_EARLY 141
		#define GPLL6_OUT_MAIN 142
		#define GPLL6_OUT_TEST 143
		#define HMSS_AHB_CLK_SRC 144
		#define HMSS_GPLL0_CLK_SRC 145
		#define HMSS_GPLL4_CLK_SRC 146
		#define HMSS_RBCPR_CLK_SRC 147
		#define MMSS_QM_CORE_CLK_SRC 148
		#define PDM2_CLK_SRC 149
		#define QSPI_SER_CLK_SRC 150
		#define SDCC1_APPS_CLK_SRC 151
		#define SDCC1_ICE_CORE_CLK_SRC 152
		#define SDCC2_APPS_CLK_SRC 153
		#define UFS_AXI_CLK_SRC 154
		#define UFS_ICE_CORE_CLK_SRC 155
		#define UFS_PHY_AUX_CLK_SRC 156
		#define UFS_UNIPRO_CORE_CLK_SRC 157
		#define USB20_MASTER_CLK_SRC 158
		#define USB20_MOCK_UTMI_CLK_SRC 159
		#define USB30_MASTER_CLK_SRC 160
		#define USB30_MOCK_UTMI_CLK_SRC 161
		#define USB3_PHY_AUX_CLK_SRC 162

		/* Block Resets */
		#define GCC_SYSTEM_NOC_BCR 0
		#define GCC_CONFIG_NOC_BCR 1
		#define GCC_IMEM_BCR 2
		#define GCC_MMSS_BCR 3
		#define GCC_PIMEM_BCR 4
		#define GCC_QDSS_BCR 5
		#define GCC_USB_30_BCR 6
		#define GCC_USB_20_BCR 7
		#define GCC_QUSB2PHY_PRIM_BCR 8
		#define GCC_QUSB2PHY_SEC_BCR 9
		#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
		#define GCC_SDCC2_BCR 11
		#define GCC_SDCC1_BCR 12
		#define GCC_BLSP1_BCR 13
		#define GCC_BLSP1_QUP1_BCR 14
		#define GCC_BLSP1_UART1_BCR 15
		#define GCC_BLSP1_QUP2_BCR 16
		#define GCC_BLSP1_UART2_BCR 17
		#define GCC_BLSP1_QUP3_BCR 18
		#define GCC_BLSP1_QUP4_BCR 19
		#define GCC_BLSP2_BCR 20
		#define GCC_BLSP2_QUP1_BCR 21
		#define GCC_BLSP2_UART1_BCR 22
		#define GCC_BLSP2_QUP2_BCR 23
		#define GCC_BLSP2_UART2_BCR 24
		#define GCC_BLSP2_QUP3_BCR 25
		#define GCC_BLSP2_QUP4_BCR 26
		#define GCC_PDM_BCR 27
		#define GCC_PRNG_BCR 28
		#define GCC_TCSR_BCR 29
		#define GCC_BOOT_ROM_BCR 30
		#define GCC_MSG_RAM_BCR 31
		#define GCC_TLMM_BCR 32
		#define GCC_MPM_BCR 33
		#define GCC_SEC_CTRL_BCR 34
		#define GCC_SPMI_BCR 35
		#define GCC_SPDM_BCR 36
		#define GCC_CE1_BCR 37
		#define GCC_BIMC_BCR 38
		#define GCC_SNOC_BUS_TIMEOUT0_BCR 39
		#define GCC_SNOC_BUS_TIMEOUT1_BCR 40
		#define GCC_SNOC_BUS_TIMEOUT3_BCR 41
		#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 42
		#define GCC_SNOC_BUS_TIMEOUT4_BCR 43
		#define GCC_PNOC_BUS_TIMEOUT0_BCR 44
		#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR 45
		#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR 46
		#define GCC_CNOC_BUS_TIMEOUT0_BCR 47
		#define GCC_CNOC_BUS_TIMEOUT2_BCR 48
		#define GCC_CNOC_BUS_TIMEOUT3_BCR 49
		#define GCC_CNOC_BUS_TIMEOUT4_BCR 50
		#define GCC_CNOC_BUS_TIMEOUT5_BCR 51
		#define GCC_CNOC_BUS_TIMEOUT6_BCR 52
		#define GCC_CNOC_BUS_TIMEOUT7_BCR 53
		#define GCC_CNOC_BUS_TIMEOUT8_BCR 54
		#define GCC_CNOC_BUS_TIMEOUT9_BCR 55
		#define GCC_CNOC_BUS_TIMEOUT10_BCR 56
		#define GCC_CNOC_BUS_TIMEOUT11_BCR 57
		#define GCC_CNOC_BUS_TIMEOUT12_BCR 58
		#define GCC_CNOC_BUS_TIMEOUT13_BCR 59
		#define GCC_CNOC_BUS_TIMEOUT14_BCR 60
		#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 61
		#define GCC_APB2JTAG_BCR 62
		#define GCC_RBCPR_CX_BCR 63
		#define GCC_RBCPR_MX_BCR 64
		#define GCC_OBT_ODT_BCR 65
		#define GCC_UFS_BCR 66
		#define GCC_VS_BCR 67
		#define GCC_AGGRE2_NOC_BCR 68
		#define GCC_DCC_BCR 69
		#define GCC_QSPI_BCR 70
		#define GCC_IPA_BCR 71
		#define GCC_GLM_BCR 72
		#define GCC_MSMPU_BCR 73
		#define GCC_QREFS_VBG_CAL_BCR 74
		#define GCC_WCSS_BCR 75
		#define GCC_GPU_BCR 76
		#define GCC_AHB2PHY_EAST_BCR 77
		#define GCC_CM_PHY_REFGEN1_BCR 78
		#define GCC_CM_PHY_REFGEN2_BCR 79
		#define GCC_SRAM_SENSOR_BCR 80

		/* GDSC */
		#define UFS_GDSC 0
		#define USB_30_GDSC 1
		#define DDR_DIM_WRAPPER_GDSC 2
		#define MMSS_GDSC 3

		#define GCC_QUSB2PHY_PRIM_BCR 0
		#define GCC_QUSB2PHY_SEC_BCR 1
		#define GCC_UFS_BCR 2
		#define GCC_USB3_DP_PHY_BCR 3
		#define GCC_USB3_PHY_BCR 4
		#define GCC_USB3PHY_PHY_BCR 5
		#define GCC_USB_20_BCR 6
		#define GCC_USB_30_BCR 7
		#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8

		/* RPM controlled clocks */
		#define RPM_CE1_CLK 1
		#define RPM_CE1_A_CLK 2
		#define RPM_CXO_CLK_SRC 3
		#define RPM_BIMC_CLK 4
		#define RPM_BIMC_A_CLK 5
		#define RPM_CNOC_CLK 6
		#define RPM_CNOC_A_CLK 7
		#define RPM_SNOC_CLK 8
		#define RPM_SNOC_A_CLK 9
		#define RPM_CNOC_PERIPH_CLK 10
		#define RPM_CNOC_PERIPH_A_CLK 11
		#define RPM_CNOC_PERIPH_KEEPALIVE_A_CLK 12
		#define RPM_LN_BB_CLK1 13
		#define RPM_LN_BB_CLK1_AO 14
		#define RPM_LN_BB_CLK1_PIN 15
		#define RPM_LN_BB_CLK1_PIN_AO 16
		#define RPM_BIMC_MSMBUS_CLK 17
		#define RPM_BIMC_MSMBUS_A_CLK 18
		#define RPM_CNOC_MSMBUS_CLK 19
		#define RPM_CNOC_MSMBUS_A_CLK 20
		#define RPM_CXO_CLK_SRC_AO 21
		#define RPM_CXO_DWC3_CLK 22
		#define RPM_CXO_LPM_CLK 23
		#define RPM_CXO_OTG_CLK 24
		#define RPM_CXO_PIL_LPASS_CLK 25
		#define RPM_CXO_PIL_SSC_CLK 26
		#define RPM_CXO_PIL_SPSS_CLK 27
		#define RPM_DIV_CLK1 28
		#define RPM_DIV_CLK1_AO 29
		#define RPM_IPA_CLK 30
		#define RPM_IPA_A_CLK 31
		#define RPM_MCD_CE1_CLK 32
		#define RPM_MMSSNOC_AXI_CLK 33
		#define RPM_MMSSNOC_AXI_A_CLK 34
		#define RPM_QCEDEV_CE1_CLK 35
		#define RPM_QCRYPTO_CE1_CLK 36
		#define RPM_QDSS_CLK 37
		#define RPM_QDSS_A_CLK 38
		#define RPM_QSEECOM_CE1_CLK 39
		#define RPM_RF_CLK2 40
		#define RPM_RF_CLK2_AO 41
		#define RPM_SCM_CE1_CLK 42
		#define RPM_SNOC_MSMBUS_CLK 43
		#define RPM_SNOC_MSMBUS_A_CLK 44
		#define RPM_AGGRE2_NOC_CLK 45
		#define RPM_AGGRE2_NOC_A_CLK 46

		#endif

include/dt-bindings/clock/qcom,gpu-msmfalcon.h

+21 −19

Original line number	Diff line number	Diff line
		@@ -14,25 +14,27 @@
		#ifndef _DT_BINDINGS_CLK_MSM_GPU_FALCON_H
		#define _DT_BINDINGS_CLK_MSM_GPU_FALCON_H

		/* Clocks */
		#define GPU_PLL0_PLL 0
		#define GPU_PLL1_PLL 1
		#define GFX3D_CLK_SRC 2
		#define RBBMTIMER_CLK_SRC 3
		#define RBCPR_CLK_SRC 4
		#define GPUCC_CXO_CLK 5
		#define GPUCC_GFX3D_CLK 6
		#define GPUCC_RBBMTIMER_CLK 7
		#define GPUCC_RBCPR_CLK 8
		#define GFX3D_CLK_SRC 0
		#define GPU_PLL0_PLL 1
		#define GPU_PLL0_PLL_OUT_AUX 2
		#define GPU_PLL0_PLL_OUT_AUX2 3
		#define GPU_PLL0_PLL_OUT_EARLY 4
		#define GPU_PLL0_PLL_OUT_MAIN 5
		#define GPU_PLL0_PLL_OUT_TEST 6
		#define GPU_PLL1_PLL 7
		#define GPU_PLL1_PLL_OUT_AUX 8
		#define GPU_PLL1_PLL_OUT_AUX2 9
		#define GPU_PLL1_PLL_OUT_EARLY 10
		#define GPU_PLL1_PLL_OUT_MAIN 11
		#define GPU_PLL1_PLL_OUT_TEST 12
		#define GPUCC_CXO_CLK 13
		#define GPUCC_GFX3D_CLK 14
		#define GPUCC_RBBMTIMER_CLK 15
		#define GPUCC_RBCPR_CLK 16
		#define RBBMTIMER_CLK_SRC 18
		#define RBCPR_CLK_SRC 19

		/* Block Reset */
		#define GPU_CC_GPU_GX_BCR 0
		#define GPU_CC_GPU_CX_BCR 1
		#define GPU_CC_RBCPR_BCR 2
		#define GPU_CC_SPDM_BCR 3

		/* GDSC */
		#define GPU_GX_GDSC 0
		#define GPU_CX_GDSC 1
		#define GPU_CX_GDSC 0
		#define GPU_GX_GDSC 1

		#endif

include/dt-bindings/clock/qcom,mmcc-msmfalcon.h

+193 −174

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