Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d345d145 authored by Osvaldo Banuelos's avatar Osvaldo Banuelos
Browse files

clk: msm: clock-osm: enable WDOG status registers for msmcobalt v2 



Enable the watchdog status registers for msmcobalt v2. This
feature must be specifically enabled in the OSM controller
of msmcobalt v2.

CRs-Fixed: 1076523
Change-Id: I1eb5c61037004e200e8f261d6e39b73028f04ab4
Signed-off-by: default avatarOsvaldo Banuelos <osvaldob@codeaurora.org>
parent 3c7400dc

drivers/clk/msm/clock-osm.c

+14 −0
Original line number Diff line number Diff line
@@ -200,6 +200,8 @@ enum clk_osm_trace_packet_id { 
#define TRACE_CTRL_EN_MASK BIT(0)

#define TRACE_CTRL_ENABLE 1

#define TRACE_CTRL_DISABLE 0

#define TRACE_CTRL_ENABLE_WDOG_STATUS	BIT(30)

#define TRACE_CTRL_ENABLE_WDOG_STATUS_MASK	BIT(30)

#define TRACE_CTRL_PACKET_TYPE_MASK BVAL(2, 1, 3)

#define TRACE_CTRL_PACKET_TYPE_SHIFT 1

#define TRACE_CTRL_PERIODIC_TRACE_EN_MASK BIT(3)
@@ -2680,6 +2682,18 @@ static int cpu_clock_osm_driver_probe(struct platform_device *pdev) 
		return rc;

	}



	if (msmcobalt_v2) {

		/* Enable OSM WDOG registers */

		clk_osm_masked_write_reg(&pwrcl_clk,

					 TRACE_CTRL_ENABLE_WDOG_STATUS,

					 TRACE_CTRL,

					 TRACE_CTRL_ENABLE_WDOG_STATUS_MASK);

		clk_osm_masked_write_reg(&perfcl_clk,

					 TRACE_CTRL_ENABLE_WDOG_STATUS,

					 TRACE_CTRL,

					 TRACE_CTRL_ENABLE_WDOG_STATUS_MASK);

	}



	/*

	 * The hmss_gpll0 clock runs at 300 MHz. Ensure it is at the correct

	 * frequency before enabling OSM. LUT index 0 is always sourced from