Commit d1f10c50 authored May 17, 2016 by Linux Build Service Account

Promotion of kernel.lnx.4.4-160516.

CRs Change ID Subject
--------------------------------------------------------------------------------------------------------------
1006303 I81b4ba8fdc2e2fe1b40f18904964098fa558989b Revert "sched: set HMP scheduler's default initial task
1005737 Idbf26d6241ab9a87e4dcea42723428289f2a869d qcom: common_log: add support to dump PMIC registers
1015036 I972c35c79327e3baa38573318ed0909d4daa9516 msm: pcie: add device and vendor ID for PCIe on msmcobal
1005737 Ibd896873bc40b723071c66ca7cf1a4bc9b38ad5e qcom: common_log: add support to dump VSENSE registers
1011333 Id4a8bca3eb77db4f998c790f1927fe373684048a defconfig: Enable CPUSS dump driver
1013213 I52ef7d45cabb20cc61fbd2fb3ef5016b041bc56c trace: cpu_freq_switch: use tracefs instead of debugfs
1014894 I8153e1c2ad9cb320a4c116593b15898dbe2f6ca2 ARM: dts: msm: Enable Silver frequency scaling up to SVS
1015361 I729af5235109cf8b09d4c89a339a4b4f14926d26 ARM: dts: msm: Disable LMH driver probe for msmhamster r
988266 Idcff59ca1483fd98173255d6258e6771d91dec19 soc: qcom: glink: Fix race condition in dummy xprt clean
1014950 Id232492bd458dac04e89a94ed5a85092223ebff6 pinctrl: qcom: Fix the base address of various GPIOs
1005738 Id2b38d93e7c12648292546592144eda1e82d76be soc: qcom: dcc: update xpu probe logic to fix failure
1006303 I0218b36b2d74974f50a173a0ac3bc59156c57624 sched: use correct Kconfig macro name CONFIG_SCHED_HMP_C
1014872 I90563104a5b6219472eaeae1964fc34b52586536 AndroidKernel.mk: additional fixes for multi-kernel tree
1015335 If83199b5990a3623b1018058d2164862352902b7 msm: sde: Add error code for unsupported rotator version
1013458 Ie15c48ae1bb34e304795607a09c753360eb015ec msm: ipa: Fix to memory leak when sending non-linear dat
1005737 I5062d65a095538a508944315e6cc06f430382bf5 qcom: common_log: add support to dump rpm code ram
1015036 I7651f2cbc53587f5b48501855260c87af2a2db01 msm: pcie: retrieve PCIe SMMU SID base from DT
1015510 I39c23b52d17994e28bd3b0d93e8e3dabdb687940 clk: msm: mdss: fix pclk_src_mux clock ops for DSI PLL o
1014782 I6913a168596b34f527f689360f93fdf15b7d2f10 ARM: dts: msm: restrict VDD_APC voltages to NOM for CPR
1005738 Ibc2de3c142b8df4ac86e4628199726750f19dac3 defconfig: arm64: enable DCC device driver
1005739 I9d644f18882729d187075e885bc2e8c02c5caf36 memory-dump: add support to allocate memory for scan dum
1008505 I5bfc16e3d6ac3c6052b8dca55b42b57480ec650e ARM: dts: msm: Add rotator clocks MNOC AHB/AXI for msmco
1015036 I42c7f545a48e6a431ccdba062399776e8c1c64f2 msm: pcie: update misc register offsets on msmcobalt
1014407 I346a909984519c2522503f842d449c6f3217b746 ARM: dts: msm: restrict VDD_GFX voltage to Nom for CPR R
1005738 Ia3187fadd4f0073e5e141595810bb8b3c7aab429 soc: qcom: dcc: update errno of dcc probe failure
1008505 I43ccff9774d098d551c4ba25ad5678fee13aca1f ARM: dts: msm: Add mnoc_ahb clock for msmcobalt
1014873 Ibd5fdd0a1f48ecd8a828d187ac86513e3f48ae6f ARM: dts: msm: Enable super speed mode support on msmcob
1009840 Id228bf7ec564669fa8e9e739e27052de0133cc4d msm: mdss: fix wb format enumeration
1005737 832905 I36eaeebf821f64dd7503ec823aca3c7aec846bd0 soc: qcom: common_log: Fix a memory leak in common_log d
1013947 Id675a541a6813a14ae0b7e1bb66670bf7467a97f arm64: enable HAVE_IRQ_TIME_ACCOUNTING for arm64
1013680 I4f82ba27becee1f3b62c410be0d00876961f9b18 ASoC: msm: Add USB audio via ADSP support
1008396 I21c2ce2b7d3bf1541a5d3580db4bc40497701095 msm: pcie: add support to get PCIe PHY init sequence fro
1015359 Ib9c79f4795d0be9ca00b3cda984ed89b61e58b02 msm: ipa3: make function names consistent with ipav2
1005738 I1d302e51693315998d915ca44f739fb58ef9e4a5 ARM: dts: msm: add DCC device on msmcobalt
1005738 Iab0a6ffa92ef6e311054756cfe85d1b2b91743c9 soc: qcom: dcc: add support for CRC mode
1006303 Iceee806479bc41d7aa32cb78b6ede59cb85fc259 defconfig: msm: enable CONFIG_SCHED_DEBUG
1015492 I20eeadbfcdae16ce9c2feb8b882471683766ec4f soc: qcom: pil: Fix error path sequence
1005738 Ic1b7b2d4d4ed4baa9e8d33a2b60c10d2e799b211 soc: qcom: dcc: change configuration programming interfa
1005738 Ic8a804250ab8b7ac501bd186d2e6f7506bb9b21a soc: qcom: dcc: add support for DCC driver
1011333 I4ed06b5602220ed4e30bd37a0633ccb3454f7d43 soc: qcom: Add snapshot of the cpuss driver
1014373 Icf950194191cbd0887740d692bb88cc650430fb8 ARM: dts: msm: Add clock rates in camera node for all bo
1015036 I44ece35ed1d8dda4d8139dfb54adc7a2e9c49383 defconfig: msm: enable PCIe bus driver in msmcobalt defc
1008076 I8bbb827e6fcddb12bf452279f5f7d60b614c2915 ARM: dts: msm: Enable VMEM node
1015026 Ief1980e2888525434e876f7cec4357403ca20cb1 msm: mdss: account for multirect when enumerating pipe f
1015036 If87bd507228476fee9713f88c06a1cf04b13f163 msm: pcie: update PCIe PHY registers and sequences for m
1015361 Id54c09e0cf2c3701c10c71d6688417d3f5d4c08e ARM: dts: msm: Disable LMH driver probe for msmcobalt ru
1005738 I773f64209b395eb9f2fc82a53d4a2f1b79b081eb soc: qcom: dcc: fix uninitialized variable bug in dcc_ll
1014894 I467f49edbc65449f29f761c6b873ca702d24fa72 ARM: dts: msm: Disable OSM vred FSM for msmcobalt
1015006 I49154af38f0c59f6add8a38ebbc06f7dcfc85373 Revert "defconfig: enable msm serial console on msmcorte
1015036 I7a41ed6dd0f78cba140a15661d44b2f6c2745e39 ARM: dts: msm: create PCIe devicetree node for msmcobalt
1013278 Id8a92b0f36f71ed50726504d1e5b3feab4cfa512 clk: msm: clock-gcc-cobalt: Update the pcie_aux_clk_src
1005738 I491bc3e41e11a5366162c65907f41f7cbcdd7809 soc: qcom: dcc: add support to send SW trigger on/off re
1005738 If76ef1325b1be623626742b0f0172a1675f21d63 qcom: memory_dump: add support to dump DCC data.
1008076 Ibda63abad6a469c0a5f738c51ee1e740d0f1ce7a defconfig: msm64: msm: Enable v4l2 video driver
1006154 I97456326a40c6d24c208307a9e8e6a55fc5b9d59 diag: Use correct index while accessing DCI channel
1005738 Idd33f53560585fdbfee4d3822fd93d6f3a365e17 soc: qcom: dcc: add check if sram data oversteps
1005737 I75be0d467c8f7c2db854987598770f9798688e51 defconfig: arm64: enable common log driver for msmcobalt
1005738 I8815f65551df0b80f7ecdcaa338a50db8d9b04f5 soc: qcom: dcc: add support for DCC XPU lock/unlock requ
1005737 Ibeb74ca064e78fe7522e46b3c32bb362082d5d24 common_log: add common_log support snapshot
1005738 I86d93bc63cf3282e360eed29732a708ee02cf6df soc: qcom: dcc: replace readx_poll_timeout with readl_po
1014989 Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533 clk: msm: clock-gcc-cobalt: Add reset capability to PCIE

Change-Id: I6717722b102189bd9490ff793dd20465a015ed2c
CRs-Fixed: 1006303, 1005739, 1005738, 1015026, 1013278, 1006154, 1005737, 1015335, 1013458, 1015510, 1015359, 1013213, 1015006, 988266, 1014407, 1014894, 1015492, 1014782, 1008505, 832905, 1014950, 1015036, 1011333, 1014872, 1014873, 1009840, 1015361, 1008396, 1014989, 1014373, 1013680, 1013947, 1008076

parents 4c3516fc c0717983

AndroidKernel.mk

+2 −2

Original line number	Diff line number	Diff line
		@@ -135,7 +135,7 @@ $(TARGET_PREBUILT_INT_KERNEL): $(KERNEL_OUT) $(KERNEL_HEADERS_INSTALL)
		$(hide) rm -rf $(KERNEL_OUT)/arch/$(KERNEL_ARCH)/boot/dts
		$(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(KERNEL_CFLAGS)
		$(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(KERNEL_CFLAGS) modules
		$(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) INSTALL_MOD_PATH=../../$(KERNEL_MODULES_INSTALL) INSTALL_MOD_STRIP=1 ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) modules_install
		$(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) INSTALL_MOD_PATH=$(BUILD_ROOT_LOC)../$(KERNEL_MODULES_INSTALL) INSTALL_MOD_STRIP=1 ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) modules_install
		$(mv-modules)
		$(clean-module-folder)

		@@ -161,7 +161,7 @@ kernelconfig: $(KERNEL_OUT) $(KERNEL_CONFIG)
		$(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) menuconfig
		env KCONFIG_NOTIMESTAMP=true \
		$(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) savedefconfig
		cp $(KERNEL_OUT)/defconfig kernel/arch/$(KERNEL_ARCH)/configs/$(KERNEL_DEFCONFIG)
		cp $(KERNEL_OUT)/defconfig $(TARGET_KERNEL_SOURCE)/arch/$(KERNEL_ARCH)/configs/$(KERNEL_DEFCONFIG)

		endif
		endif

Documentation/devicetree/bindings/cpuss_dump/cpuss_dump.txt

0 → 100644

+27 −0

Original line number	Diff line number	Diff line
		CPU Subsystem Dump Driver

		The CPU Subsystem dump driver is used to dump various hardware entities
		like the instruction and data tlbs or the unified tlbs etc. to an
		allocated buffer. This allows the data to be analysed in case of corruption.

		Required Properties for the cpuss_dump node:
		-compatible = "qcom,cpuss-dump";

		All child nodes of cpuss_dump node are interpreted as the various hardware
		entities which need to be dumped.

		Required properties of the dump nodes

		- qcom,dump-node: phandle to the acutal cpuss hardware entity present
		in the cpu map
		- qcom,dump-id: The ID within the data dump table where this entry needs to
		be added.

		Example:
		msm_cpuss_dump {
		compatible = "qcom,cpuss-dump";
		qcom,itlb_dump100 {
		qcom,dump-node = <&L1_itlb_100>;
		qcom,dump-id = <34>;
		};
		};

Documentation/devicetree/bindings/pci/msm_pcie.txt

+13 −0

Original line number	Diff line number	Diff line
		@@ -73,6 +73,8 @@ Optional Properties:
		- qcom,n-fts: The number of fast training sequences sent when the link state
		is changed from L0s to L0.
		- qcom,pcie-phy-ver: version of PCIe PHY.
		- qcom,phy-sequence: The initialization sequence to bring up the PCIe PHY.
		Should be specified in groups (offset, value, delay).
		- qcom,use-19p2mhz-aux-clk: The frequency of PCIe AUX clock is 19.2MHz.
		- qcom,ep-wakeirq: The endpoint will issue wake signal when it is up, and the
		root complex has the capability to enumerate the endpoint for this case.
		@@ -84,6 +86,8 @@ Optional Properties:
		complex nodes, and is the only property needed in that case.
		- qcom,common-phy: There is a common phy for all the Root Complexes.
		- qcom,smmu-exist: PCIe uses a SMMU.
		- qcom,smmu-sid-base: The base SMMU SID that PCIe bus driver will use to calculate
		and assign for each endpoint.
		- qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become
		stable after power on, before de-assert the PERST to the endpoint.
		- qcom,cpl-timeout: Completion timeout value. This value specifies the time range
		@@ -185,6 +189,14 @@ Example:
		"msi_20", "msi_21", "msi_22", "msi_23",
		"msi_24", "msi_25", "msi_26", "msi_27",
		"msi_28", "msi_29", "msi_30", "msi_31";

		qcom,phy-sequence = <0x804 0x01 0x00
		0x034 0x14 0x00
		0x138 0x30 0x00
		0x048 0x0f 0x00
		0x15c 0x06 0x00
		0x090 0x01 0x00
		0x808 0x03 0x00>;
		perst-gpio = <&msmgpio 70 0>;
		wake-gpio = <&msmgpio 69 0>;
		clkreq-gpio = <&msmgpio 68 0>;
		@@ -230,6 +242,7 @@ Example:
		qcom,tlp-rd-size = <0x5>;
		qcom,common-phy;
		qcom,smmu-exist;
		qcom,smmu-sid-base = <0x1480>;
		qcom,ep-latency = <100>;
		qcom,cpl-timeout = <0x2>;

Documentation/devicetree/bindings/soc/qcom/dcc.txt

0 → 100644

+42 −0

Original line number	Diff line number	Diff line
		* Data Capture and Compare (DCC)

		DCC (Data Capture and Compare) is a DMA engine, which is used to save
		configuration data or system memory contents during catastrophic failure or
		SW trigger.
		It can also perform CRC over the same configuration or memory space.

		Required properties:

		- compatible : name of the component used for driver matching, should be
		"qcom,dcc"

		- reg : physical base address and length of the register set(s), SRAM and XPU
		of the component.

		- reg-names : names corresponding to each reg property value.

		Optional properties:

		- qcom,save-reg: boolean, To save dcc registers state in memory after dcc
		enable and disable

		- qcom,data-sink: string, To specify default data sink for dcc, should be one
		of the following:
		"atb" : To send captured data over ATB to a trace sink
		"sram" : To save captured data in dcc internal SRAM.

		Example:

		dcc: dcc@4b3000 {
		compatible = "qcom,dcc";
		reg = <0x4b3000 0x1000>,
		<0x4b4000 0x2000>,
		<0x4b0000 0x1>;
		reg-names = "dcc-base", "dcc-ram-base", "dcc-xpu-base";

		clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>;
		clock-names = "dcc_clk";

		qcom,save-reg;
		};

Documentation/scheduler/sched-hmp.txt

+1 −1

Original line number	Diff line number	Diff line
		@@ -1101,7 +1101,7 @@ tasks - they may be woken up on busy CPUs.

		Appears at: /proc/sys/kernel/sched_init_task_load

		Default value: 100
		Default value: 15

		This tunable is a percentage. When a task is first created it has no
		history, so the task load tracking mechanism cannot determine a