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Commit d1726dc6 authored by Rajesh Kemisetti's avatar Rajesh Kemisetti Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Add support for A509 GPU 



Add new GPU ID and required initial settings
to support Graphics functionality on SDM636.

Change-Id: If8a801c20c7f60618797ccd440d2d739f6817708
Signed-off-by: default avatarRajesh Kemisetti <rajeshk@codeaurora.org>
parent 2c178b1b

drivers/gpu/msm/adreno-gpulist.h

+17 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2002,2007-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2002,2007-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -299,6 +299,22 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A509,

		.core = 5,

		.major = 0,

		.minor = 9,

		.patchid = ANY_ID,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a512_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_size = (SZ_256K + SZ_16K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A508,

		.core = 5,

drivers/gpu/msm/adreno.h

+3 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2008-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -170,6 +170,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A505 = 505,

	ADRENO_REV_A506 = 506,

	ADRENO_REV_A508 = 508,

	ADRENO_REV_A509 = 509,

	ADRENO_REV_A510 = 510,

	ADRENO_REV_A512 = 512,

	ADRENO_REV_A530 = 530,
@@ -1006,6 +1007,7 @@ static inline int adreno_is_a5xx(struct adreno_device *adreno_dev) 
ADRENO_TARGET(a505, ADRENO_REV_A505)

ADRENO_TARGET(a506, ADRENO_REV_A506)

ADRENO_TARGET(a508, ADRENO_REV_A508)

ADRENO_TARGET(a509, ADRENO_REV_A509)

ADRENO_TARGET(a510, ADRENO_REV_A510)

ADRENO_TARGET(a512, ADRENO_REV_A512)

ADRENO_TARGET(a530, ADRENO_REV_A530)

drivers/gpu/msm/adreno_a5xx.c

+14 −6
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ static const struct adreno_vbif_platform a5xx_vbif_platforms[] = { 
	{ adreno_is_a530, a530_vbif },

	{ adreno_is_a512, a540_vbif },

	{ adreno_is_a510, a530_vbif },

	{ adreno_is_a509, a540_vbif },

	{ adreno_is_a508, a530_vbif },

	{ adreno_is_a505, a530_vbif },

	{ adreno_is_a506, a530_vbif },
@@ -161,6 +162,7 @@ static const struct { 
	{ adreno_is_a530, a530_efuse_speed_bin },

	{ adreno_is_a505, a530_efuse_speed_bin },

	{ adreno_is_a512, a530_efuse_speed_bin },

	{ adreno_is_a509, a530_efuse_speed_bin },

	{ adreno_is_a508, a530_efuse_speed_bin },

};
@@ -201,7 +203,8 @@ static void a5xx_platform_setup(struct adreno_device *adreno_dev) 
		gpudev->vbif_xin_halt_ctrl0_mask =

				A510_VBIF_XIN_HALT_CTRL0_MASK;

	} else if (adreno_is_a540(adreno_dev) ||

		adreno_is_a512(adreno_dev)) {

		adreno_is_a512(adreno_dev) ||

		adreno_is_a509(adreno_dev)) {

		gpudev->snapshot_data->sect_sizes->cp_merciu = 1024;

	}
@@ -539,7 +542,8 @@ static void a5xx_regulator_disable(struct adreno_device *adreno_dev) 
	unsigned int reg;

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	if (adreno_is_a512(adreno_dev) || adreno_is_a508(adreno_dev))

	if (adreno_is_a512(adreno_dev) || adreno_is_a509(adreno_dev) ||

		adreno_is_a508(adreno_dev))

		return;



	/* If feature is not supported or not enabled */
@@ -1199,6 +1203,7 @@ static const struct { 
	{ adreno_is_a540, a540_hwcg_regs, ARRAY_SIZE(a540_hwcg_regs) },

	{ adreno_is_a530, a530_hwcg_regs, ARRAY_SIZE(a530_hwcg_regs) },

	{ adreno_is_a512, a512_hwcg_regs, ARRAY_SIZE(a512_hwcg_regs) },

	{ adreno_is_a509, a512_hwcg_regs, ARRAY_SIZE(a512_hwcg_regs) },

	{ adreno_is_a510, a510_hwcg_regs, ARRAY_SIZE(a510_hwcg_regs) },

	{ adreno_is_a505, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },

	{ adreno_is_a506, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },
@@ -1651,7 +1656,7 @@ static void a5xx_clk_set_options(struct adreno_device *adreno_dev, 
{



	if (!adreno_is_a540(adreno_dev) && !adreno_is_a512(adreno_dev) &&

		!adreno_is_a508(adreno_dev))

		!adreno_is_a508(adreno_dev) && !adreno_is_a509(adreno_dev))

		return;



	/* Handle clock settings for GFX PSCBCs */
@@ -1957,7 +1962,8 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
		kgsl_regwrite(device, A5XX_CP_MERCIU_SIZE, 0x20);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A);

	} else if (adreno_is_a540(adreno_dev) || adreno_is_a512(adreno_dev)) {

	} else if (adreno_is_a540(adreno_dev) || adreno_is_a512(adreno_dev) ||

			adreno_is_a509(adreno_dev)) {

		kgsl_regwrite(device, A5XX_CP_MEQ_THRESHOLDS, 0x40);

		kgsl_regwrite(device, A5XX_CP_MERCIU_SIZE, 0x400);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060);
@@ -1976,7 +1982,8 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
	if (adreno_is_a505_or_a506(adreno_dev) || adreno_is_a508(adreno_dev))

		kgsl_regwrite(device, A5XX_PC_DBG_ECO_CNTL,

						(0x100 << 11 | 0x100 << 22));

	else if (adreno_is_a510(adreno_dev) || adreno_is_a512(adreno_dev))

	else if (adreno_is_a510(adreno_dev) || adreno_is_a512(adreno_dev) ||

			adreno_is_a509(adreno_dev))

		kgsl_regwrite(device, A5XX_PC_DBG_ECO_CNTL,

						(0x200 << 11 | 0x200 << 22));

	else
@@ -2069,7 +2076,8 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
			kgsl_regwrite(device, A5XX_TPL1_MODE_CNTL, bit << 7);

			kgsl_regwrite(device, A5XX_RB_MODE_CNTL, bit << 1);

			if (adreno_is_a540(adreno_dev) ||

				adreno_is_a512(adreno_dev))

				adreno_is_a512(adreno_dev) ||

				adreno_is_a509(adreno_dev))

				kgsl_regwrite(device, A5XX_UCHE_DBG_ECO_CNTL_2,

					bit);

		}