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Commit d11ac1d2 authored by Dinh Nguyen's avatar Dinh Nguyen
Browse files

ARM: dts: socfpga: rename gpio nodes 



Since the Synopsys GPIO IP can support multiple ports of varying widths, it
would make more sense to have the GPIO node DTS entry as this:

gpio0: gpio@ff708000{
	porta{
	};
};

Also, this is documented in the snps-dwapb-gpio.txt.

Suggested-by: default avatarDoug Anderson <dianders@chromium.org>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
parent 3a4356c0

arch/arm/boot/dts/socfpga.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -547,7 +547,7 @@ 
			status = "disabled";

		};



		gpio@ff708000 {

		gpio0: gpio@ff708000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";
@@ -555,7 +555,7 @@ 
			clocks = <&per_base_clk>;

			status = "disabled";



			gpio0: gpio-controller@0 {

			porta: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;
@@ -567,7 +567,7 @@ 
			};

		};



		gpio@ff709000 {

		gpio1: gpio@ff709000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";
@@ -575,7 +575,7 @@ 
			clocks = <&per_base_clk>;

			status = "disabled";



			gpio1: gpio-controller@0 {

			portb: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;
@@ -587,7 +587,7 @@ 
			};

		};



		gpio@ff70a000 {

		gpio2: gpio@ff70a000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";
@@ -595,7 +595,7 @@ 
			clocks = <&per_base_clk>;

			status = "disabled";



			gpio2: gpio-controller@0 {

			portc: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;