Loading drivers/gpu/drm/msm/dba_bridge.c +5 −2 Original line number Diff line number Diff line Loading @@ -132,7 +132,9 @@ static void _dba_bridge_pre_enable(struct drm_bridge *bridge) } d_bridge = to_dba_bridge(bridge); if (d_bridge->ops.power_on) /* Skip power_on calling when splash is enabled in bootloader. */ if ((d_bridge->ops.power_on) && (!d_bridge->cont_splash_enabled)) d_bridge->ops.power_on(d_bridge->dba_ctx, true, 0); } Loading Loading @@ -193,7 +195,8 @@ static void _dba_bridge_enable(struct drm_bridge *bridge) video_cfg.scaninfo, video_cfg.ar, video_cfg.vic); } if (d_bridge->ops.video_on) { /* Skip video_on calling if splash is enabled in bootloader. */ if ((d_bridge->ops.video_on) && (!d_bridge->cont_splash_enabled)) { rc = d_bridge->ops.video_on(d_bridge->dba_ctx, true, &video_cfg, 0); if (rc) Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +8 −13 Original line number Diff line number Diff line Loading @@ -1608,14 +1608,15 @@ int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl, bool cont_splash_enabled) } mutex_lock(&dsi_ctrl->ctrl_lock); rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1); if (!cont_splash_enabled) { rc = dsi_ctrl_check_state( dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1); if (rc) { pr_err("[DSI_%d] Controller state check failed, rc=%d\n", pr_err("[DSI_%d] Ctrl state check failed, rc=%d\n", dsi_ctrl->index, rc); goto error; } if (!cont_splash_enabled) { dsi_ctrl->hw.ops.setup_lane_map(&dsi_ctrl->hw, &dsi_ctrl->host_config.lane_map); Loading Loading @@ -1970,12 +1971,6 @@ error: return rc; } void dsi_ctrl_update_power_state(struct dsi_ctrl *dsi_ctrl, enum dsi_power_state state) { dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_POWER_STATE_CHANGE, state); } /** * dsi_ctrl_set_tpg_state() - enable/disable test pattern on the controller * @dsi_ctrl: DSI controller handle. Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h +0 −10 Original line number Diff line number Diff line Loading @@ -404,16 +404,6 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags); int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl, enum dsi_power_state state); /** * dsi_ctrl_update_power_state() - update power state for dsi controller * @dsi_ctrl: DSI controller handle. * @state: Power state. * * Update power state for DSI controller. * */ void dsi_ctrl_update_power_state(struct dsi_ctrl *dsi_ctrl, enum dsi_power_state state); /** * dsi_ctrl_set_cmd_engine_state() - set command engine state * @dsi_ctrl: DSI Controller handle. Loading drivers/gpu/drm/msm/dsi-staging/dsi_display.c +22 −20 Original line number Diff line number Diff line Loading @@ -236,6 +236,12 @@ static int dsi_display_phy_power_on(struct dsi_display *display) int i; struct dsi_display_ctrl *ctrl; /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip phy power on\n"); return rc; } /* Sequence does not matter for split dsi usecases */ for (i = 0; i < display->ctrl_count; i++) { Loading Loading @@ -292,6 +298,12 @@ static int dsi_display_ctrl_core_clk_on(struct dsi_display *display) int i; struct dsi_display_ctrl *m_ctrl, *ctrl; /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip core clk on calling\n"); return rc; } /* * In case of split DSI usecases, the clock for master controller should * be enabled before the other controller. Master controller in the Loading Loading @@ -334,6 +346,12 @@ static int dsi_display_ctrl_link_clk_on(struct dsi_display *display) int i; struct dsi_display_ctrl *m_ctrl, *ctrl; /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip ctrl link clk on calling\n"); return rc; } /* * In case of split DSI usecases, the clock for master controller should * be enabled before the other controller. Master controller in the Loading Loading @@ -2827,28 +2845,12 @@ int dsi_dsiplay_setup_splash_resource(struct dsi_display *display) if (!ctrl) return -EINVAL; dsi_pwr_enable_regulator(&ctrl->ctrl->pwr_info.host_pwr, true); dsi_pwr_enable_regulator(&ctrl->ctrl->pwr_info.digital, true); dsi_pwr_enable_regulator(&ctrl->phy->pwr_info.phy_pwr, true); ret = dsi_clk_enable_core_clks(&ctrl->ctrl->clk_info.core_clks, true); if (ret) { SDE_ERROR("failed to set core clk for dsi, ret = %d\n", ret); return -EINVAL; } ret = dsi_clk_enable_link_clks(&ctrl->ctrl->clk_info.link_clks, true); ret = dsi_ctrl_set_power_state(ctrl->ctrl, DSI_CTRL_POWER_LINK_CLK_ON); if (ret) { SDE_ERROR("failed to set link clk for dsi, ret = %d\n", ret); return -EINVAL; SDE_ERROR("calling dsi_ctrl_set_power_state failed\n"); return ret; } dsi_ctrl_update_power_state(ctrl->ctrl, DSI_CTRL_POWER_LINK_CLK_ON); } return ret; Loading Loading
drivers/gpu/drm/msm/dba_bridge.c +5 −2 Original line number Diff line number Diff line Loading @@ -132,7 +132,9 @@ static void _dba_bridge_pre_enable(struct drm_bridge *bridge) } d_bridge = to_dba_bridge(bridge); if (d_bridge->ops.power_on) /* Skip power_on calling when splash is enabled in bootloader. */ if ((d_bridge->ops.power_on) && (!d_bridge->cont_splash_enabled)) d_bridge->ops.power_on(d_bridge->dba_ctx, true, 0); } Loading Loading @@ -193,7 +195,8 @@ static void _dba_bridge_enable(struct drm_bridge *bridge) video_cfg.scaninfo, video_cfg.ar, video_cfg.vic); } if (d_bridge->ops.video_on) { /* Skip video_on calling if splash is enabled in bootloader. */ if ((d_bridge->ops.video_on) && (!d_bridge->cont_splash_enabled)) { rc = d_bridge->ops.video_on(d_bridge->dba_ctx, true, &video_cfg, 0); if (rc) Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +8 −13 Original line number Diff line number Diff line Loading @@ -1608,14 +1608,15 @@ int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl, bool cont_splash_enabled) } mutex_lock(&dsi_ctrl->ctrl_lock); rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1); if (!cont_splash_enabled) { rc = dsi_ctrl_check_state( dsi_ctrl, DSI_CTRL_OP_HOST_INIT, 0x1); if (rc) { pr_err("[DSI_%d] Controller state check failed, rc=%d\n", pr_err("[DSI_%d] Ctrl state check failed, rc=%d\n", dsi_ctrl->index, rc); goto error; } if (!cont_splash_enabled) { dsi_ctrl->hw.ops.setup_lane_map(&dsi_ctrl->hw, &dsi_ctrl->host_config.lane_map); Loading Loading @@ -1970,12 +1971,6 @@ error: return rc; } void dsi_ctrl_update_power_state(struct dsi_ctrl *dsi_ctrl, enum dsi_power_state state) { dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_POWER_STATE_CHANGE, state); } /** * dsi_ctrl_set_tpg_state() - enable/disable test pattern on the controller * @dsi_ctrl: DSI controller handle. Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h +0 −10 Original line number Diff line number Diff line Loading @@ -404,16 +404,6 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags); int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl, enum dsi_power_state state); /** * dsi_ctrl_update_power_state() - update power state for dsi controller * @dsi_ctrl: DSI controller handle. * @state: Power state. * * Update power state for DSI controller. * */ void dsi_ctrl_update_power_state(struct dsi_ctrl *dsi_ctrl, enum dsi_power_state state); /** * dsi_ctrl_set_cmd_engine_state() - set command engine state * @dsi_ctrl: DSI Controller handle. Loading
drivers/gpu/drm/msm/dsi-staging/dsi_display.c +22 −20 Original line number Diff line number Diff line Loading @@ -236,6 +236,12 @@ static int dsi_display_phy_power_on(struct dsi_display *display) int i; struct dsi_display_ctrl *ctrl; /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip phy power on\n"); return rc; } /* Sequence does not matter for split dsi usecases */ for (i = 0; i < display->ctrl_count; i++) { Loading Loading @@ -292,6 +298,12 @@ static int dsi_display_ctrl_core_clk_on(struct dsi_display *display) int i; struct dsi_display_ctrl *m_ctrl, *ctrl; /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip core clk on calling\n"); return rc; } /* * In case of split DSI usecases, the clock for master controller should * be enabled before the other controller. Master controller in the Loading Loading @@ -334,6 +346,12 @@ static int dsi_display_ctrl_link_clk_on(struct dsi_display *display) int i; struct dsi_display_ctrl *m_ctrl, *ctrl; /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip ctrl link clk on calling\n"); return rc; } /* * In case of split DSI usecases, the clock for master controller should * be enabled before the other controller. Master controller in the Loading Loading @@ -2827,28 +2845,12 @@ int dsi_dsiplay_setup_splash_resource(struct dsi_display *display) if (!ctrl) return -EINVAL; dsi_pwr_enable_regulator(&ctrl->ctrl->pwr_info.host_pwr, true); dsi_pwr_enable_regulator(&ctrl->ctrl->pwr_info.digital, true); dsi_pwr_enable_regulator(&ctrl->phy->pwr_info.phy_pwr, true); ret = dsi_clk_enable_core_clks(&ctrl->ctrl->clk_info.core_clks, true); if (ret) { SDE_ERROR("failed to set core clk for dsi, ret = %d\n", ret); return -EINVAL; } ret = dsi_clk_enable_link_clks(&ctrl->ctrl->clk_info.link_clks, true); ret = dsi_ctrl_set_power_state(ctrl->ctrl, DSI_CTRL_POWER_LINK_CLK_ON); if (ret) { SDE_ERROR("failed to set link clk for dsi, ret = %d\n", ret); return -EINVAL; SDE_ERROR("calling dsi_ctrl_set_power_state failed\n"); return ret; } dsi_ctrl_update_power_state(ctrl->ctrl, DSI_CTRL_POWER_LINK_CLK_ON); } return ret; Loading