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Commit cc7059b5 authored by James Yang's avatar James Yang Committed by Benjamin Herrenschmidt
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powerpc/math-emu: Fix load/store indexed emulation 



Load/store indexed instructions where the index register RA=R0, such
as "lfdx f1,0,r3", are not illegal.

Load/store indexed with update instructions where the index register
RA=R0, such as "lfdux f1,0,r3", are invalid, and, to be consistent
with existing math-emu behavior for other invalid instruction forms,
will signal as illegal.

Signed-off-by: default avatarJames Yang <James.Yang@freescale.com>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 5f20be44

arch/powerpc/math-emu/math.c

+5 −10
Original line number Diff line number Diff line
@@ -380,21 +380,16 @@ do_mathemu(struct pt_regs *regs) 
	case XE:

		idx = (insn >> 16) & 0x1f;

		op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);

		if (!idx) {

			if (((insn >> 1) & 0x3ff) == STFIWX)

				op1 = (void *)(regs->gpr[(insn >> 11) & 0x1f]);

			else

				goto illegal;

		} else {

			op1 = (void *)(regs->gpr[idx] + regs->gpr[(insn >> 11) & 0x1f]);

		}



		op1 = (void *)((idx ? regs->gpr[idx] : 0)

				+ regs->gpr[(insn >> 11) & 0x1f]);

		break;



	case XEU:

		idx = (insn >> 16) & 0x1f;

		if (!idx)

			goto illegal;

		op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);

		op1 = (void *)((idx ? regs->gpr[idx] : 0)

		op1 = (void *)(regs->gpr[idx]

				+ regs->gpr[(insn >> 11) & 0x1f]);

		break;