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Commit cc60a1a4 authored by Kumar Gala's avatar Kumar Gala
Browse files

ARM: dts: msm: split out msm8660 and msm8960 soc into dts include 



Pull the SoC device tree bits into their own files so other boards based
on these SoCs can include them and reduce duplication across a number of
boards.

Signed-off-by: default avatarKumar Gala <galak@codeaurora.org>
parent 38dbfb59

arch/arm/boot/dts/qcom-msm8660-surf.dts

+1 −58
Original line number Original line Diff line number Diff line 
/dts-v1/;

#include "qcom-msm8660.dtsi"



/include/ "skeleton.dtsi"



#include <dt-bindings/clock/qcom,gcc-msm8660.h>





/ {

/ {

	model = "Qualcomm MSM8660 SURF";

	model = "Qualcomm MSM8660 SURF";

	compatible = "qcom,msm8660-surf", "qcom,msm8660";

	compatible = "qcom,msm8660-surf", "qcom,msm8660";

	interrupt-parent = <&intc>;



	intc: interrupt-controller@2080000 {

		compatible = "qcom,msm-8660-qgic";

		interrupt-controller;

		#interrupt-cells = <3>;

		reg = < 0x02080000 0x1000 >,

		      < 0x02081000 0x1000 >;

	};



	timer@2000000 {

		compatible = "qcom,scss-timer", "qcom,msm-timer";

		interrupts = <1 0 0x301>,

			     <1 1 0x301>,

			     <1 2 0x301>;

		reg = <0x02000000 0x100>;

		clock-frequency = <27000000>,

				  <32768>;

		cpu-offset = <0x40000>;

	};



	msmgpio: gpio@800000 {

		compatible = "qcom,msm-gpio";

		reg = <0x00800000 0x4000>;

		gpio-controller;

		#gpio-cells = <2>;

		ngpio = <173>;

		interrupts = <0 16 0x4>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};



	gcc: clock-controller@900000 {

		compatible = "qcom,gcc-msm8660";

		#clock-cells = <1>;

		#reset-cells = <1>;

		reg = <0x900000 0x4000>;

	};



	serial@19c40000 {

		compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

		reg = <0x19c40000 0x1000>,

		      <0x19c00000 0x1000>;

		interrupts = <0 195 0x0>;

		clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;

		clock-names = "core", "iface";

	};



	qcom,ssbi@500000 {

		compatible = "qcom,ssbi";

		reg = <0x500000 0x1000>;

		qcom,controller-type = "pmic-arbiter";

	};

};
 
};

arch/arm/boot/dts/qcom-msm8660.dtsi

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+63 −0
Original line number Original line Diff line number Diff line 
/dts-v1/;



/include/ "skeleton.dtsi"



#include <dt-bindings/clock/qcom,gcc-msm8660.h>



/ {

	model = "Qualcomm MSM8660";

	compatible = "qcom,msm8660";

	interrupt-parent = <&intc>;



	intc: interrupt-controller@2080000 {

		compatible = "qcom,msm-8660-qgic";

		interrupt-controller;

		#interrupt-cells = <3>;

		reg = < 0x02080000 0x1000 >,

		      < 0x02081000 0x1000 >;

	};



	timer@2000000 {

		compatible = "qcom,scss-timer", "qcom,msm-timer";

		interrupts = <1 0 0x301>,

			     <1 1 0x301>,

			     <1 2 0x301>;

		reg = <0x02000000 0x100>;

		clock-frequency = <27000000>,

				  <32768>;

		cpu-offset = <0x40000>;

	};



	msmgpio: gpio@800000 {

		compatible = "qcom,msm-gpio";

		reg = <0x00800000 0x4000>;

		gpio-controller;

		#gpio-cells = <2>;

		ngpio = <173>;

		interrupts = <0 16 0x4>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};



	gcc: clock-controller@900000 {

		compatible = "qcom,gcc-msm8660";

		#clock-cells = <1>;

		#reset-cells = <1>;

		reg = <0x900000 0x4000>;

	};



	serial@19c40000 {

		compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

		reg = <0x19c40000 0x1000>,

		      <0x19c00000 0x1000>;

		interrupts = <0 195 0x0>;

		clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;

		clock-names = "core", "iface";

	};



	qcom,ssbi@500000 {

		compatible = "qcom,ssbi";

		reg = <0x500000 0x1000>;

		qcom,controller-type = "pmic-arbiter";

	};

};

arch/arm/boot/dts/qcom-msm8960-cdp.dts

+1 −65
Original line number Original line Diff line number Diff line 
/dts-v1/;

#include "qcom-msm8960.dtsi"



/include/ "skeleton.dtsi"



#include <dt-bindings/clock/qcom,gcc-msm8960.h>





/ {

/ {

	model = "Qualcomm MSM8960 CDP";

	model = "Qualcomm MSM8960 CDP";

	compatible = "qcom,msm8960-cdp", "qcom,msm8960";

	compatible = "qcom,msm8960-cdp", "qcom,msm8960";

	interrupt-parent = <&intc>;



	intc: interrupt-controller@2000000 {

		compatible = "qcom,msm-qgic2";

		interrupt-controller;

		#interrupt-cells = <3>;

		reg = < 0x02000000 0x1000 >,

		      < 0x02002000 0x1000 >;

	};



	timer@200a000 {

		compatible = "qcom,kpss-timer", "qcom,msm-timer";

		interrupts = <1 1 0x301>,

			     <1 2 0x301>,

			     <1 3 0x301>;

		reg = <0x0200a000 0x100>;

		clock-frequency = <27000000>,

				  <32768>;

		cpu-offset = <0x80000>;

	};



	msmgpio: gpio@800000 {

		compatible = "qcom,msm-gpio";

		gpio-controller;

		#gpio-cells = <2>;

		ngpio = <150>;

		interrupts = <0 16 0x4>;

		interrupt-controller;

		#interrupt-cells = <2>;

		reg = <0x800000 0x4000>;

	};



	gcc: clock-controller@900000 {

		compatible = "qcom,gcc-msm8960";

		#clock-cells = <1>;

		#reset-cells = <1>;

		reg = <0x900000 0x4000>;

	};



	clock-controller@4000000 {

		compatible = "qcom,mmcc-msm8960";

		reg = <0x4000000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	serial@16440000 {

		compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

		reg = <0x16440000 0x1000>,

		      <0x16400000 0x1000>;

		interrupts = <0 154 0x0>;

		clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;

		clock-names = "core", "iface";

	};



	qcom,ssbi@500000 {

		compatible = "qcom,ssbi";

		reg = <0x500000 0x1000>;

		qcom,controller-type = "pmic-arbiter";

	};

};
 
};

arch/arm/boot/dts/qcom-msm8960.dtsi

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+70 −0
Original line number Original line Diff line number Diff line 
/dts-v1/;



/include/ "skeleton.dtsi"



#include <dt-bindings/clock/qcom,gcc-msm8960.h>



/ {

	model = "Qualcomm MSM8960";

	compatible = "qcom,msm8960";

	interrupt-parent = <&intc>;



	intc: interrupt-controller@2000000 {

		compatible = "qcom,msm-qgic2";

		interrupt-controller;

		#interrupt-cells = <3>;

		reg = < 0x02000000 0x1000 >,

		      < 0x02002000 0x1000 >;

	};



	timer@200a000 {

		compatible = "qcom,kpss-timer", "qcom,msm-timer";

		interrupts = <1 1 0x301>,

			     <1 2 0x301>,

			     <1 3 0x301>;

		reg = <0x0200a000 0x100>;

		clock-frequency = <27000000>,

				  <32768>;

		cpu-offset = <0x80000>;

	};



	msmgpio: gpio@800000 {

		compatible = "qcom,msm-gpio";

		gpio-controller;

		#gpio-cells = <2>;

		ngpio = <150>;

		interrupts = <0 16 0x4>;

		interrupt-controller;

		#interrupt-cells = <2>;

		reg = <0x800000 0x4000>;

	};



	gcc: clock-controller@900000 {

		compatible = "qcom,gcc-msm8960";

		#clock-cells = <1>;

		#reset-cells = <1>;

		reg = <0x900000 0x4000>;

	};



	clock-controller@4000000 {

		compatible = "qcom,mmcc-msm8960";

		reg = <0x4000000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	serial@16440000 {

		compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

		reg = <0x16440000 0x1000>,

		      <0x16400000 0x1000>;

		interrupts = <0 154 0x0>;

		clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;

		clock-names = "core", "iface";

	};



	qcom,ssbi@500000 {

		compatible = "qcom,ssbi";

		reg = <0x500000 0x1000>;

		qcom,controller-type = "pmic-arbiter";

	};

};