Loading Documentation/devicetree/bindings/arm/msm/clock-controller-dummy.txt +5 −0 Original line number Diff line number Diff line Loading @@ -9,9 +9,14 @@ Required properties: - #clock_cells: Must be <1>. This will allow the common clock device tree framework to recognize _this_ device node as a clock provider. Optional properties: - #reset-cells: Must be <1>. This will allow the common reset device tree framework to recognize _this_ device node as a reset controller provider. Example: clock_rpm: qcom,rpmcc { compatible = "qcom,dummycc"; #clock-cells = <1>; #reset-cells = <1>; }; drivers/clk/qcom/clk-branch.c +48 −0 Original line number Diff line number Diff line Loading @@ -125,15 +125,62 @@ static int clk_branch_enable(struct clk_hw *hw) return clk_branch_toggle(hw, true, clk_branch_check_halt); } static int clk_cbcr_set_flags(struct regmap *regmap, unsigned int reg, unsigned long flags) { u32 cbcr_val; regmap_read(regmap, reg, &cbcr_val); switch (flags) { case CLKFLAG_PERIPH_OFF_SET: cbcr_val |= BIT(12); break; case CLKFLAG_PERIPH_OFF_CLEAR: cbcr_val &= ~BIT(12); break; case CLKFLAG_RETAIN_PERIPH: cbcr_val |= BIT(13); break; case CLKFLAG_NORETAIN_PERIPH: cbcr_val &= ~BIT(13); break; case CLKFLAG_RETAIN_MEM: cbcr_val |= BIT(14); break; case CLKFLAG_NORETAIN_MEM: cbcr_val &= ~BIT(14); break; default: return -EINVAL; } regmap_write(regmap, reg, cbcr_val); /* Make sure power is enabled/disabled before returning. */ mb(); udelay(1); return 0; } static void clk_branch_disable(struct clk_hw *hw) { clk_branch_toggle(hw, false, clk_branch_check_halt); } static int clk_branch_set_flags(struct clk_hw *hw, unsigned flags) { struct clk_branch *br = to_clk_branch(hw); return clk_cbcr_set_flags(br->clkr.regmap, br->halt_reg, flags); } const struct clk_ops clk_branch_ops = { .enable = clk_branch_enable, .disable = clk_branch_disable, .is_enabled = clk_is_enabled_regmap, .set_flags = clk_branch_set_flags, }; EXPORT_SYMBOL_GPL(clk_branch_ops); Loading @@ -151,6 +198,7 @@ const struct clk_ops clk_branch2_ops = { .enable = clk_branch2_enable, .disable = clk_branch2_disable, .is_enabled = clk_is_enabled_regmap, .set_flags = clk_branch_set_flags, }; EXPORT_SYMBOL_GPL(clk_branch2_ops); Loading drivers/clk/qcom/clk-branch.h +9 −0 Original line number Diff line number Diff line Loading @@ -73,4 +73,13 @@ extern const struct clk_ops clk_branch_simple_ops; #define to_clk_gate2(_hw) \ container_of(to_clk_regmap(_hw), struct clk_gate2, clkr) enum branch_mem_flags { CLKFLAG_RETAIN_PERIPH, CLKFLAG_NORETAIN_PERIPH, CLKFLAG_RETAIN_MEM, CLKFLAG_NORETAIN_MEM, CLKFLAG_PERIPH_OFF_SET, CLKFLAG_PERIPH_OFF_CLEAR, }; #endif drivers/clk/qcom/clk-dummy.c +51 −4 Original line number Diff line number Diff line Loading @@ -15,14 +15,18 @@ #include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/reset-controller.h> struct clk_dummy { struct clk_hw hw; struct reset_controller_dev reset; unsigned long rrate; }; #define to_clk_dummy(_hw) container_of(_hw, struct clk_dummy, hw) #define RESET_MAX 100 static int dummy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { Loading Loading @@ -51,22 +55,48 @@ static unsigned long dummy_clk_recalc_rate(struct clk_hw *hw, return dummy->rrate; } static int dummy_clk_set_flags(struct clk_hw *hw, unsigned flags) { return 0; } struct clk_ops clk_dummy_ops = { .set_rate = dummy_clk_set_rate, .round_rate = dummy_clk_round_rate, .recalc_rate = dummy_clk_recalc_rate, .set_flags = dummy_clk_set_flags, }; EXPORT_SYMBOL_GPL(clk_dummy_ops); static int dummy_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { pr_debug("%s\n", __func__); return 0; } static int dummy_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { pr_debug("%s\n", __func__); return 0; } static struct reset_control_ops dummy_reset_ops = { .assert = dummy_reset_assert, .deassert = dummy_reset_deassert, }; /** * clk_register_dummy - register dummy clock with the * clock framework * @dev: device that is registering this clock * @name: name of this clock * @flags: framework-specific flags * @node: device node */ static struct clk *clk_register_dummy(struct device *dev, const char *name, unsigned long flags) unsigned long flags, struct device_node *node) { struct clk_dummy *dummy; struct clk *clk; Loading @@ -85,8 +115,20 @@ static struct clk *clk_register_dummy(struct device *dev, const char *name, /* register the clock */ clk = clk_register(dev, &dummy->hw); if (IS_ERR(clk)) if (IS_ERR(clk)) { kfree(dummy); return clk; } dummy->reset.of_node = node; dummy->reset.ops = &dummy_reset_ops; dummy->reset.nr_resets = RESET_MAX; if (reset_controller_register(&dummy->reset)) pr_err("Failed to register reset controller for %s\n", name); else pr_info("Successfully registered a dummy reset controller for %s\n", name); return clk; } Loading @@ -101,10 +143,15 @@ static void of_dummy_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); clk = clk_register_dummy(NULL, clk_name, 0); clk = clk_register_dummy(NULL, clk_name, 0, node); if (!IS_ERR(clk)) of_clk_add_provider(node, of_clk_src_simple_get, clk); else { pr_err("Failed to register dummy clock controller for %s\n", clk_name); return; } pr_info("%s: Dummy clock registered\n", clk_name); pr_info("Successfully registered dummy clock for %s\n", clk_name); } CLK_OF_DECLARE(dummy_clk, "qcom,dummycc", of_dummy_clk_setup); Loading
Documentation/devicetree/bindings/arm/msm/clock-controller-dummy.txt +5 −0 Original line number Diff line number Diff line Loading @@ -9,9 +9,14 @@ Required properties: - #clock_cells: Must be <1>. This will allow the common clock device tree framework to recognize _this_ device node as a clock provider. Optional properties: - #reset-cells: Must be <1>. This will allow the common reset device tree framework to recognize _this_ device node as a reset controller provider. Example: clock_rpm: qcom,rpmcc { compatible = "qcom,dummycc"; #clock-cells = <1>; #reset-cells = <1>; };
drivers/clk/qcom/clk-branch.c +48 −0 Original line number Diff line number Diff line Loading @@ -125,15 +125,62 @@ static int clk_branch_enable(struct clk_hw *hw) return clk_branch_toggle(hw, true, clk_branch_check_halt); } static int clk_cbcr_set_flags(struct regmap *regmap, unsigned int reg, unsigned long flags) { u32 cbcr_val; regmap_read(regmap, reg, &cbcr_val); switch (flags) { case CLKFLAG_PERIPH_OFF_SET: cbcr_val |= BIT(12); break; case CLKFLAG_PERIPH_OFF_CLEAR: cbcr_val &= ~BIT(12); break; case CLKFLAG_RETAIN_PERIPH: cbcr_val |= BIT(13); break; case CLKFLAG_NORETAIN_PERIPH: cbcr_val &= ~BIT(13); break; case CLKFLAG_RETAIN_MEM: cbcr_val |= BIT(14); break; case CLKFLAG_NORETAIN_MEM: cbcr_val &= ~BIT(14); break; default: return -EINVAL; } regmap_write(regmap, reg, cbcr_val); /* Make sure power is enabled/disabled before returning. */ mb(); udelay(1); return 0; } static void clk_branch_disable(struct clk_hw *hw) { clk_branch_toggle(hw, false, clk_branch_check_halt); } static int clk_branch_set_flags(struct clk_hw *hw, unsigned flags) { struct clk_branch *br = to_clk_branch(hw); return clk_cbcr_set_flags(br->clkr.regmap, br->halt_reg, flags); } const struct clk_ops clk_branch_ops = { .enable = clk_branch_enable, .disable = clk_branch_disable, .is_enabled = clk_is_enabled_regmap, .set_flags = clk_branch_set_flags, }; EXPORT_SYMBOL_GPL(clk_branch_ops); Loading @@ -151,6 +198,7 @@ const struct clk_ops clk_branch2_ops = { .enable = clk_branch2_enable, .disable = clk_branch2_disable, .is_enabled = clk_is_enabled_regmap, .set_flags = clk_branch_set_flags, }; EXPORT_SYMBOL_GPL(clk_branch2_ops); Loading
drivers/clk/qcom/clk-branch.h +9 −0 Original line number Diff line number Diff line Loading @@ -73,4 +73,13 @@ extern const struct clk_ops clk_branch_simple_ops; #define to_clk_gate2(_hw) \ container_of(to_clk_regmap(_hw), struct clk_gate2, clkr) enum branch_mem_flags { CLKFLAG_RETAIN_PERIPH, CLKFLAG_NORETAIN_PERIPH, CLKFLAG_RETAIN_MEM, CLKFLAG_NORETAIN_MEM, CLKFLAG_PERIPH_OFF_SET, CLKFLAG_PERIPH_OFF_CLEAR, }; #endif
drivers/clk/qcom/clk-dummy.c +51 −4 Original line number Diff line number Diff line Loading @@ -15,14 +15,18 @@ #include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/reset-controller.h> struct clk_dummy { struct clk_hw hw; struct reset_controller_dev reset; unsigned long rrate; }; #define to_clk_dummy(_hw) container_of(_hw, struct clk_dummy, hw) #define RESET_MAX 100 static int dummy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { Loading Loading @@ -51,22 +55,48 @@ static unsigned long dummy_clk_recalc_rate(struct clk_hw *hw, return dummy->rrate; } static int dummy_clk_set_flags(struct clk_hw *hw, unsigned flags) { return 0; } struct clk_ops clk_dummy_ops = { .set_rate = dummy_clk_set_rate, .round_rate = dummy_clk_round_rate, .recalc_rate = dummy_clk_recalc_rate, .set_flags = dummy_clk_set_flags, }; EXPORT_SYMBOL_GPL(clk_dummy_ops); static int dummy_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { pr_debug("%s\n", __func__); return 0; } static int dummy_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { pr_debug("%s\n", __func__); return 0; } static struct reset_control_ops dummy_reset_ops = { .assert = dummy_reset_assert, .deassert = dummy_reset_deassert, }; /** * clk_register_dummy - register dummy clock with the * clock framework * @dev: device that is registering this clock * @name: name of this clock * @flags: framework-specific flags * @node: device node */ static struct clk *clk_register_dummy(struct device *dev, const char *name, unsigned long flags) unsigned long flags, struct device_node *node) { struct clk_dummy *dummy; struct clk *clk; Loading @@ -85,8 +115,20 @@ static struct clk *clk_register_dummy(struct device *dev, const char *name, /* register the clock */ clk = clk_register(dev, &dummy->hw); if (IS_ERR(clk)) if (IS_ERR(clk)) { kfree(dummy); return clk; } dummy->reset.of_node = node; dummy->reset.ops = &dummy_reset_ops; dummy->reset.nr_resets = RESET_MAX; if (reset_controller_register(&dummy->reset)) pr_err("Failed to register reset controller for %s\n", name); else pr_info("Successfully registered a dummy reset controller for %s\n", name); return clk; } Loading @@ -101,10 +143,15 @@ static void of_dummy_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); clk = clk_register_dummy(NULL, clk_name, 0); clk = clk_register_dummy(NULL, clk_name, 0, node); if (!IS_ERR(clk)) of_clk_add_provider(node, of_clk_src_simple_get, clk); else { pr_err("Failed to register dummy clock controller for %s\n", clk_name); return; } pr_info("%s: Dummy clock registered\n", clk_name); pr_info("Successfully registered dummy clock for %s\n", clk_name); } CLK_OF_DECLARE(dummy_clk, "qcom,dummycc", of_dummy_clk_setup);