Commit cb6db5d8 authored May 03, 2017 by Maya Erez

ARM: dts: msm: enable SMMU stage1 for 11AD devices on msm8998



Set smmu-s1-en to enable SMMU stage1.
This change also sets SMMU base address and size, required when
SMMU stage1 is enabled.

Change-Id: I30f4528c665c7623cb56de0773a0a3da2b4c21bf
Signed-off-by: Maya Erez <merez@codeaurora.org>

parent 8d601310

arch/arm/boot/dts/qcom/msm8998.dtsi

+4 −0

Original line number	Diff line number	Diff line
		@@ -3200,6 +3200,10 @@
		<&clock_gcc clk_rf_clk3_pin>;
		clock-names = "rf_clk3_clk", "rf_clk3_pin_clk";
		qcom,smmu-support;
		qcom,smmu-s1-en;
		qcom,smmu-fast-map;
		qcom,smmu-coherent;
		qcom,smmu-mapping = <0x20000000 0xe0000000>;
		status = "disabled";
		};