Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cb0dd4bc authored by Tatenda Chipeperekwa's avatar Tatenda Chipeperekwa
Browse files

msm: mdss: dp: update Clock Recovery phase of link training 



Update TRAINING_PATTERN_SET then TRAINING_LANEx_SET in the
Clock Recovery phase of link training as this is the sequence
mandated in the display port specification.

CRs-Fixed: 1076516
Change-Id: I7aa157d9377799563180792fe5d31a22a7aff0e1
Signed-off-by: default avatarTatenda Chipeperekwa <tatendac@codeaurora.org>
parent a9494a84

drivers/video/fbdev/msm/mdss_dp_aux.c

+2 −2
Original line number Diff line number Diff line
@@ -1174,8 +1174,9 @@ static int dp_start_link_train_1(struct mdss_dp_drv_pdata *ep) 
	pr_debug("Entered++");



	dp_host_train_set(ep, 0x01); /* train_1 */

	dp_voltage_pre_emphasise_set(ep);

	dp_cap_lane_rate_set(ep);

	dp_train_pattern_set_write(ep, 0x21); /* train_1 */

	dp_voltage_pre_emphasise_set(ep);



	tries = 0;

	old_v_level = ep->v_level;
@@ -1336,7 +1337,6 @@ int mdss_dp_link_train(struct mdss_dp_drv_pdata *dp) 
train_start:

	dp->v_level = 0; /* start from default level */

	dp->p_level = 0;

	dp_cap_lane_rate_set(dp);

	mdss_dp_config_ctrl(dp);



	mdss_dp_state_ctrl(&dp->ctrl_io, 0);