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Commit c9b4dc70 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "Merge branch 'android-4.4@e76c0fa' into branch 'msm-4.4'"

parents a21b8a6a e0a0b484

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 4

PATCHLEVEL = 4

SUBLEVEL = 71

SUBLEVEL = 72

EXTRAVERSION =

NAME = Blurry Fish Butt

arch/arm/kvm/init.S

+2 −3
Original line number Diff line number Diff line
@@ -110,7 +110,6 @@ __do_hyp_init: 
	@  - Write permission implies XN: disabled

	@  - Instruction cache: enabled

	@  - Data/Unified cache: enabled

	@  - Memory alignment checks: enabled

	@  - MMU: enabled (this code must be run from an identity mapping)

	mrc	p15, 4, r0, c1, c0, 0	@ HSCR

	ldr	r2, =HSCTLR_MASK
@@ -118,8 +117,8 @@ __do_hyp_init: 
	mrc	p15, 0, r1, c1, c0, 0	@ SCTLR

	ldr	r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)

	and	r1, r1, r2

 ARM(	ldr	r2, =(HSCTLR_M | HSCTLR_A)			)

 THUMB(	ldr	r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE)		)

 ARM(	ldr	r2, =(HSCTLR_M)					)

 THUMB(	ldr	r2, =(HSCTLR_M | HSCTLR_TE)			)

	orr	r1, r1, r2

	orr	r0, r0, r1

	isb

arch/arm/kvm/mmu.c

+3 −0
Original line number Diff line number Diff line
@@ -876,6 +876,9 @@ static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache *cache 
	pmd_t *pmd;



	pud = stage2_get_pud(kvm, cache, addr);

	if (!pud)

		return NULL;



	if (pud_none(*pud)) {

		if (!cache)

			return NULL;

arch/arm64/include/asm/asm-uaccess.h

0 → 100644
+13 −0
Original line number Diff line number Diff line 
#ifndef __ASM_ASM_UACCESS_H

#define __ASM_ASM_UACCESS_H



/*

 * Remove the address tag from a virtual address, if present.

 */

	.macro	clear_address_tag, dst, addr

	tst	\addr, #(1 << 55)

	bic	\dst, \addr, #(0xff << 56)

	csel	\dst, \dst, \addr, eq

	.endm



#endif

arch/arm64/include/asm/barrier.h

+14 −4
Original line number Diff line number Diff line
@@ -44,23 +44,33 @@ 


#define smp_store_release(p, v)						\

do {									\

	union { typeof(*p) __val; char __c[1]; } __u =			\

		{ .__val = (__force typeof(*p)) (v) }; 			\

	compiletime_assert_atomic_type(*p);				\

	switch (sizeof(*p)) {						\

	case 1:								\

		asm volatile ("stlrb %w1, %0"				\

				: "=Q" (*p) : "r" (v) : "memory");	\

				: "=Q" (*p)				\

				: "r" (*(__u8 *)__u.__c)		\

				: "memory");				\

		break;							\

	case 2:								\

		asm volatile ("stlrh %w1, %0"				\

				: "=Q" (*p) : "r" (v) : "memory");	\

				: "=Q" (*p)				\

				: "r" (*(__u16 *)__u.__c)		\

				: "memory");				\

		break;							\

	case 4:								\

		asm volatile ("stlr %w1, %0"				\

				: "=Q" (*p) : "r" (v) : "memory");	\

				: "=Q" (*p)				\

				: "r" (*(__u32 *)__u.__c)		\

				: "memory");				\

		break;							\

	case 8:								\

		asm volatile ("stlr %1, %0"				\

				: "=Q" (*p) : "r" (v) : "memory");	\

				: "=Q" (*p)				\

				: "r" (*(__u64 *)__u.__c)		\

				: "memory");				\

		break;							\

	}								\

} while (0)