sparc32: Remove cypress cpu support. (c7020eb4) · Commits · e / devices / android_kernel_sony_msm8998

arch/sparc/include/asm/cypress.h

deleted100644 → 0

+0 −79

Original line number	Diff line number	Diff line
		/*
		* cypress.h: Cypress module specific definitions and defines.
		*
		* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
		*/

		#ifndef _SPARC_CYPRESS_H
		#define _SPARC_CYPRESS_H

		/* Cypress chips have %psr 'impl' of '0001' and 'vers' of '0001'. */

		/* The MMU control register fields on the Sparc Cypress 604/605 MMU's.
		*
		* ---------------------------------------------------------------
		* \|implvers\| MCA \| MCM \|MV\| MID \|BM\| C\|RSV\|MR\|CM\|CL\|CE\|RSV\|NF\|ME\|
		* ---------------------------------------------------------------
		* 31 24 23-22 21-20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
		*
		* MCA: MultiChip Access -- Used for configuration of multiple
		* CY7C604/605 cache units.
		* MCM: MultiChip Mask -- Again, for multiple cache unit config.
		* MV: MultiChip Valid -- Indicates MCM and MCA have valid settings.
		* MID: ModuleID -- Unique processor ID for MBus transactions. (605 only)
		* BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
		* C: Cacheable -- Indicates whether accesses are cacheable while
		* the MMU is off. 0=no 1=yes
		* MR: MemoryReflection -- Indicates whether the bus attached to the
		* MBus supports memory reflection. 0=no 1=yes (605 only)
		* CM: CacheMode -- Indicates whether the cache is operating in write
		* through or copy-back mode. 0=write-through 1=copy-back
		* CL: CacheLock -- Indicates if the entire cache is locked or not.
		* 0=not-locked 1=locked (604 only)
		* CE: CacheEnable -- Is the virtual cache on? 0=no 1=yes
		* NF: NoFault -- Do faults generate traps? 0=yes 1=no
		* ME: MmuEnable -- Is the MMU doing translations? 0=no 1=yes
		*/

		#define CYPRESS_MCA 0x00c00000
		#define CYPRESS_MCM 0x00300000
		#define CYPRESS_MVALID 0x00080000
		#define CYPRESS_MIDMASK 0x00078000 /* Only on 605 */
		#define CYPRESS_BMODE 0x00004000
		#define CYPRESS_ACENABLE 0x00002000
		#define CYPRESS_MRFLCT 0x00000800 /* Only on 605 */
		#define CYPRESS_CMODE 0x00000400
		#define CYPRESS_CLOCK 0x00000200 /* Only on 604 */
		#define CYPRESS_CENABLE 0x00000100
		#define CYPRESS_NFAULT 0x00000002
		#define CYPRESS_MENABLE 0x00000001

		static inline void cypress_flush_page(unsigned long page)
		{
		__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
		"r" (page), "i" (ASI_M_FLUSH_PAGE));
		}

		static inline void cypress_flush_segment(unsigned long addr)
		{
		__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
		"r" (addr), "i" (ASI_M_FLUSH_SEG));
		}

		static inline void cypress_flush_region(unsigned long addr)
		{
		__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
		"r" (addr), "i" (ASI_M_FLUSH_REGION));
		}

		static inline void cypress_flush_context(void)
		{
		__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
		"i" (ASI_M_FLUSH_CTX));
		}

		/* XXX Displacement flushes for buggy chips and initial testing
		* XXX go here.
		*/

		#endif /* !(_SPARC_CYPRESS_H) */

arch/sparc/include/asm/elf_32.h

+3 −9

Original line number	Diff line number	Diff line
		@@ -118,15 +118,9 @@ typedef struct {
		instruction set this cpu supports. This can NOT be done in userspace
		on Sparc. */

		/* Most sun4m's have them all.
		* XXX This is gross, set some global variable at boot time. -DaveM
		*/
		#define ELF_HWCAP ((HWCAP_SPARC_FLUSH \| HWCAP_SPARC_STBAR \| \
		HWCAP_SPARC_SWAP \| \
		((srmmu_modtype != Cypress && \
		srmmu_modtype != Cypress_vE && \
		srmmu_modtype != Cypress_vD) ? \
		HWCAP_SPARC_MULDIV : 0)))
		/* Most sun4m's have them all. */
		#define ELF_HWCAP (HWCAP_SPARC_FLUSH \| HWCAP_SPARC_STBAR \| \
		HWCAP_SPARC_SWAP \| HWCAP_SPARC_MULDIV)

		/* This yields a string that ld.so will use to load implementation
		specific libraries for optimization. This is more specific in

arch/sparc/include/asm/mbus.h

+0 −4

Original line number	Diff line number	Diff line
		@@ -8,14 +8,10 @@
		#define _SPARC_MBUS_H

		#include <asm/ross.h> /* HyperSparc stuff */
		#include <asm/cypress.h> /* Cypress Chips */
		#include <asm/viking.h> /* Ugh, bug city... */

		enum mbus_module {
		HyperSparc = 0,
		Cypress = 1,
		Cypress_vE = 2,
		Cypress_vD = 3,
		Swift_ok = 4,
		Swift_bad_c = 5,
		Swift_lots_o_bugs = 6,

arch/sparc/kernel/head_32.S

+0 −15

Original line number	Diff line number	Diff line
		@@ -746,21 +746,6 @@ sun4d_init:
		/* Fall through to sun4m_init */

		sun4m_init:
		/* XXX Fucking Cypress... */
		lda [%g0] ASI_M_MMUREGS, %g5
		srl %g5, 28, %g4

		cmp %g4, 1
		bne 1f
		srl %g5, 24, %g4

		and %g4, 0xf, %g4
		cmp %g4, 7 /* This would be a HyperSparc. */

		bne 2f
		nop

		1:

		#define PATCH_IT(dst, src) \
		set (dst), %g5; \

arch/sparc/kernel/irq_32.c

+0 −11

Original line number	Diff line number	Diff line
		@@ -23,14 +23,6 @@
		#include "kernel.h"
		#include "irq.h"

		#ifdef CONFIG_SMP
		#define SMP_NOP2 "nop; nop;\n\t"
		#define SMP_NOP3 "nop; nop; nop;\n\t"
		#else
		#define SMP_NOP2
		#define SMP_NOP3
		#endif /* SMP */

		/* platform specific irq setup */
		struct sparc_config sparc_config;

		@@ -41,7 +33,6 @@ unsigned long arch_local_irq_save(void)

		__asm__ __volatile__(
		"rd %%psr, %0\n\t"
		SMP_NOP3 /* Sun4m + Cypress + SMP bug */
		"or %0, %2, %1\n\t"
		"wr %1, 0, %%psr\n\t"
		"nop; nop; nop\n"
		@@ -59,7 +50,6 @@ void arch_local_irq_enable(void)

		__asm__ __volatile__(
		"rd %%psr, %0\n\t"
		SMP_NOP3 /* Sun4m + Cypress + SMP bug */
		"andn %0, %1, %0\n\t"
		"wr %0, 0, %%psr\n\t"
		"nop; nop; nop\n"
		@@ -76,7 +66,6 @@ void arch_local_irq_restore(unsigned long old_psr)
		__asm__ __volatile__(
		"rd %%psr, %0\n\t"
		"and %2, %1, %2\n\t"
		SMP_NOP2 /* Sun4m + Cypress + SMP bug */
		"andn %0, %1, %0\n\t"
		"wr %0, %2, %%psr\n\t"
		"nop; nop; nop\n"