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Commit c57c2ffb authored by David S. Miller's avatar David S. Miller
Browse files

[SPARC64]: Kill asm-sparc64/pbm.h 



Everything it contains can be hidden in pci_impl.h

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 63c3f460

arch/sparc64/kernel/ebus.c

+2 −1
Original line number Diff line number Diff line
@@ -13,16 +13,17 @@ 
#include <linux/string.h>

#include <linux/interrupt.h>

#include <linux/delay.h>

#include <linux/pci.h>



#include <asm/system.h>

#include <asm/page.h>

#include <asm/pbm.h>

#include <asm/ebus.h>

#include <asm/oplib.h>

#include <asm/prom.h>

#include <asm/of_device.h>

#include <asm/bpp.h>

#include <asm/irq.h>

#include <asm/io.h>



/* EBUS dma library. */

arch/sparc64/kernel/pci.c

+1 −1
Original line number Diff line number Diff line
@@ -14,12 +14,12 @@ 
#include <linux/sched.h>

#include <linux/capability.h>

#include <linux/errno.h>

#include <linux/pci.h>

#include <linux/msi.h>

#include <linux/irq.h>

#include <linux/init.h>



#include <asm/uaccess.h>

#include <asm/pbm.h>

#include <asm/pgtable.h>

#include <asm/irq.h>

#include <asm/ebus.h>

arch/sparc64/kernel/pci_common.c

+1 −1
Original line number Diff line number Diff line
@@ -9,9 +9,9 @@ 
#include <linux/pci.h>

#include <linux/device.h>



#include <asm/pbm.h>

#include <asm/prom.h>

#include <asm/of_device.h>

#include <asm/oplib.h>



#include "pci_impl.h"

arch/sparc64/kernel/pci_fire.c

+0 −1
Original line number Diff line number Diff line
@@ -7,7 +7,6 @@ 
#include <linux/slab.h>

#include <linux/init.h>



#include <asm/pbm.h>

#include <asm/oplib.h>

#include <asm/prom.h>

arch/sparc64/kernel/pci_impl.h

+113 −0
Original line number Diff line number Diff line
@@ -8,8 +8,119 @@ 


#include <linux/types.h>

#include <linux/spinlock.h>

#include <linux/pci.h>

#include <linux/msi.h>

#include <asm/io.h>

#include <asm/prom.h>

#include <asm/iommu.h>



/* The abstraction used here is that there are PCI controllers,

 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules

 * underneath.  Each PCI bus module uses an IOMMU (shared by both

 * PBMs of a controller, or per-PBM), and if a streaming buffer

 * is present, each PCI bus module has it's own. (ie. the IOMMU

 * might be shared between PBMs, the STC is never shared)

 * Furthermore, each PCI bus module controls it's own autonomous

 * PCI bus.

 */



#define PCI_STC_FLUSHFLAG_INIT(STC) \

	(*((STC)->strbuf_flushflag) = 0UL)

#define PCI_STC_FLUSHFLAG_SET(STC) \

	(*((STC)->strbuf_flushflag) != 0UL)



struct pci_controller_info;



struct pci_pbm_info {

	struct pci_pbm_info		*next;

	int				index;



	/* PCI controller we sit under. */

	struct pci_controller_info	*parent;



	/* Physical address base of controller registers. */

	unsigned long			controller_regs;



	/* Physical address base of PBM registers. */

	unsigned long			pbm_regs;



	/* Physical address of DMA sync register, if any.  */

	unsigned long			sync_reg;



	/* Opaque 32-bit system bus Port ID. */

	u32				portid;



	/* Opaque 32-bit handle used for hypervisor calls.  */

	u32				devhandle;



	/* Chipset version information. */

	int				chip_type;

#define PBM_CHIP_TYPE_SABRE		1

#define PBM_CHIP_TYPE_PSYCHO		2

#define PBM_CHIP_TYPE_SCHIZO		3

#define PBM_CHIP_TYPE_SCHIZO_PLUS	4

#define PBM_CHIP_TYPE_TOMATILLO		5

	int				chip_version;

	int				chip_revision;



	/* Name used for top-level resources. */

	char				*name;



	/* OBP specific information. */

	struct device_node		*prom_node;

	u64				ino_bitmap;



	/* PBM I/O and Memory space resources. */

	struct resource			io_space;

	struct resource			mem_space;



	/* Base of PCI Config space, can be per-PBM or shared. */

	unsigned long			config_space;



	/* State of 66MHz capabilities on this PBM. */

	int				is_66mhz_capable;

	int				all_devs_66mhz;



#ifdef CONFIG_PCI_MSI

	/* MSI info.  */

	u32				msiq_num;

	u32				msiq_ent_count;

	u32				msiq_first;

	u32				msiq_first_devino;

	u32				msi_num;

	u32				msi_first;

	u32				msi_data_mask;

	u32				msix_data_width;

	u64				msi32_start;

	u64				msi64_start;

	u32				msi32_len;

	u32				msi64_len;

	void				*msi_queues;

	unsigned long			*msi_bitmap;

	int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,

			     struct msi_desc *entry);

	void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);

#endif /* !(CONFIG_PCI_MSI) */



	/* This PBM's streaming buffer. */

	struct strbuf			stc;



	/* IOMMU state, potentially shared by both PBM segments. */

	struct iommu			*iommu;



	/* Now things for the actual PCI bus probes. */

	unsigned int			pci_first_busno;

	unsigned int			pci_last_busno;

	struct pci_bus			*pci_bus;

	void (*scan_bus)(struct pci_pbm_info *);

	struct pci_ops			*pci_ops;

};



struct pci_controller_info {

	/* The PCI bus modules controlled by us. */

	struct pci_pbm_info		pbm_A;

	struct pci_pbm_info		pbm_B;

};



extern struct pci_pbm_info *pci_pbm_root;

extern unsigned long pci_memspace_mask;
@@ -17,6 +128,8 @@ extern unsigned long pci_memspace_mask; 
extern int pci_num_pbms;



/* PCI bus scanning and fixup support. */

extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize,

				 u32 dma_offset, u32 dma_addr_mask);

extern void pci_get_pbm_props(struct pci_pbm_info *pbm);

extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm);

extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm);