Loading arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -113,6 +113,7 @@ reg = <0xcd00000 0x40000>; #iommu-cells = <1>; qcom,register-save; qcom,no-smr-check; qcom,skip-init; #global-interrupts = <2>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, Loading arch/arm/boot/dts/qcom/msmcobalt.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -2776,6 +2776,8 @@ &gdsc_bimc_smmu { clock-names = "bus_clk"; clocks = <&clock_mmss clk_mmss_bimc_smmu_axi_clk>; proxy-supply = <&gdsc_bimc_smmu>; qcom,proxy-consumer-enable; status = "ok"; }; Loading drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c +5 −5 Original line number Diff line number Diff line Loading @@ -509,7 +509,7 @@ static unsigned long dsi_pll_get_vco_rate(struct clk *c) 16); /* OUTDIV_1:0 field is (log(outdiv, 2)) */ outdiv = MDSS_PLL_REG_R(pll->pll_base, PLL_OUTDIV); outdiv = MDSS_PLL_REG_R(pll->pll_base, PLL_PLL_OUTDIV_RATE); outdiv &= 0x3; outdiv = 1 << outdiv; Loading @@ -521,12 +521,12 @@ static unsigned long dsi_pll_get_vco_rate(struct clk *c) multiplier = 1 << 18; pll_freq = dec * (ref_clk * 2); tmp64 = (ref_clk * 2 * frac); pll_freq += do_div(tmp64, multiplier); pll_freq += div_u64(tmp64, multiplier); vco_rate = do_div(pll_freq, outdiv); vco_rate = div_u64(pll_freq, outdiv); pr_debug("dec=0x%x\n, frac=0x%x, outdiv=%d, vco=%lu\n", dec, frac, outdiv, (unsigned long)vco_rate); pr_debug("dec=0x%x, frac=0x%x, outdiv=%d, vco=%llu\n", dec, frac, outdiv, vco_rate); (void)mdss_pll_resource_enable(pll, false); Loading Loading
arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -113,6 +113,7 @@ reg = <0xcd00000 0x40000>; #iommu-cells = <1>; qcom,register-save; qcom,no-smr-check; qcom,skip-init; #global-interrupts = <2>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, Loading
arch/arm/boot/dts/qcom/msmcobalt.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -2776,6 +2776,8 @@ &gdsc_bimc_smmu { clock-names = "bus_clk"; clocks = <&clock_mmss clk_mmss_bimc_smmu_axi_clk>; proxy-supply = <&gdsc_bimc_smmu>; qcom,proxy-consumer-enable; status = "ok"; }; Loading
drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c +5 −5 Original line number Diff line number Diff line Loading @@ -509,7 +509,7 @@ static unsigned long dsi_pll_get_vco_rate(struct clk *c) 16); /* OUTDIV_1:0 field is (log(outdiv, 2)) */ outdiv = MDSS_PLL_REG_R(pll->pll_base, PLL_OUTDIV); outdiv = MDSS_PLL_REG_R(pll->pll_base, PLL_PLL_OUTDIV_RATE); outdiv &= 0x3; outdiv = 1 << outdiv; Loading @@ -521,12 +521,12 @@ static unsigned long dsi_pll_get_vco_rate(struct clk *c) multiplier = 1 << 18; pll_freq = dec * (ref_clk * 2); tmp64 = (ref_clk * 2 * frac); pll_freq += do_div(tmp64, multiplier); pll_freq += div_u64(tmp64, multiplier); vco_rate = do_div(pll_freq, outdiv); vco_rate = div_u64(pll_freq, outdiv); pr_debug("dec=0x%x\n, frac=0x%x, outdiv=%d, vco=%lu\n", dec, frac, outdiv, (unsigned long)vco_rate); pr_debug("dec=0x%x, frac=0x%x, outdiv=%d, vco=%llu\n", dec, frac, outdiv, vco_rate); (void)mdss_pll_resource_enable(pll, false); Loading