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Commit c42d0bb4 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Jeevan Shriram
Browse files

clk: msm: clock-gcc-cobalt: Add new hw_ctl_clk type UFS clocks 



Add new UFS clocks to support enabling/disabling the hardware
dynamic gating for their corresponding branch clocks.

CRs-Fixed: 1012355
Change-Id: I4836ad8a775b0ec0375e37d27fcbe380e661a7b2
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 8516d6c2

drivers/clk/msm/clock-gcc-cobalt.c

+48 −0
Original line number Diff line number Diff line
@@ -1996,6 +1996,17 @@ static struct branch_clk gcc_ufs_axi_clk = { 
	},

};



static struct hw_ctl_clk gcc_ufs_axi_hw_ctl_clk = {

	.cbcr_reg = GCC_UFS_AXI_CBCR,

	.base = &virt_base,

	.c = {

		.dbg_name = "gcc_ufs_axi_hw_ctl_clk",

		.parent = &gcc_ufs_axi_clk.c,

		.ops = &clk_ops_branch_hw_ctl,

		CLK_INIT(gcc_ufs_axi_hw_ctl_clk.c),

	},

};



static struct branch_clk gcc_ufs_ice_core_clk = {

	.cbcr_reg = GCC_UFS_ICE_CORE_CBCR,

	.has_sibling = 0,
@@ -2008,6 +2019,17 @@ static struct branch_clk gcc_ufs_ice_core_clk = { 
	},

};



static struct hw_ctl_clk gcc_ufs_ice_core_hw_ctl_clk = {

	.cbcr_reg = GCC_UFS_ICE_CORE_CBCR,

	.base = &virt_base,

	.c = {

		.dbg_name = "gcc_ufs_ice_core_hw_ctl_clk",

		.parent = &gcc_ufs_ice_core_clk.c,

		.ops = &clk_ops_branch_hw_ctl,

		CLK_INIT(gcc_ufs_ice_core_hw_ctl_clk.c),

	},

};



static struct branch_clk gcc_ufs_phy_aux_clk = {

	.cbcr_reg = GCC_UFS_PHY_AUX_CBCR,

	.has_sibling = 0,
@@ -2020,6 +2042,17 @@ static struct branch_clk gcc_ufs_phy_aux_clk = { 
	},

};



static struct hw_ctl_clk gcc_ufs_phy_aux_hw_ctl_clk = {

	.cbcr_reg = GCC_UFS_PHY_AUX_CBCR,

	.base = &virt_base,

	.c = {

		.dbg_name = "gcc_ufs_phy_aux_hw_ctl_clk",

		.parent = &gcc_ufs_phy_aux_clk.c,

		.ops = &clk_ops_branch_hw_ctl,

		CLK_INIT(gcc_ufs_phy_aux_hw_ctl_clk.c),

	},

};



static struct gate_clk gcc_ufs_rx_symbol_0_clk = {

	.en_reg = GCC_UFS_RX_SYMBOL_0_CBCR,

	.en_mask = BIT(0),
@@ -2068,6 +2101,17 @@ static struct branch_clk gcc_ufs_unipro_core_clk = { 
	},

};



static struct hw_ctl_clk gcc_ufs_unipro_core_hw_ctl_clk = {

	.cbcr_reg = GCC_UFS_UNIPRO_CORE_CBCR,

	.base = &virt_base,

	.c = {

		.dbg_name = "gcc_ufs_unipro_core_hw_ctl_clk",

		.parent = &gcc_ufs_unipro_core_clk.c,

		.ops = &clk_ops_branch_hw_ctl,

		CLK_INIT(gcc_ufs_unipro_core_hw_ctl_clk.c),

	},

};



static struct branch_clk gcc_usb30_master_clk = {

	.cbcr_reg = GCC_USB30_MASTER_CBCR,

	.bcr_reg = GCC_USB_30_BCR,
@@ -2642,12 +2686,16 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { 
	CLK_LIST(gcc_tsif_ref_clk),

	CLK_LIST(gcc_ufs_ahb_clk),

	CLK_LIST(gcc_ufs_axi_clk),

	CLK_LIST(gcc_ufs_axi_hw_ctl_clk),

	CLK_LIST(gcc_ufs_ice_core_clk),

	CLK_LIST(gcc_ufs_ice_core_hw_ctl_clk),

	CLK_LIST(gcc_ufs_phy_aux_clk),

	CLK_LIST(gcc_ufs_phy_aux_hw_ctl_clk),

	CLK_LIST(gcc_ufs_rx_symbol_0_clk),

	CLK_LIST(gcc_ufs_rx_symbol_1_clk),

	CLK_LIST(gcc_ufs_tx_symbol_0_clk),

	CLK_LIST(gcc_ufs_unipro_core_clk),

	CLK_LIST(gcc_ufs_unipro_core_hw_ctl_clk),

	CLK_LIST(gcc_usb30_master_clk),

	CLK_LIST(gcc_usb30_mock_utmi_clk),

	CLK_LIST(gcc_usb30_sleep_clk),

include/dt-bindings/clock/msm-clocks-cobalt.h

+4 −0
Original line number Diff line number Diff line
@@ -228,14 +228,18 @@ 
#define clk_gcc_tsif_ref_clk			0x8f1ed2c2

#define clk_gcc_ufs_ahb_clk			0x1914bb84

#define clk_gcc_ufs_axi_clk			0x47c743a7

#define clk_gcc_ufs_axi_hw_ctl_clk		0x69385b45

#define clk_gcc_ufs_ice_core_clk		0x310b0710

#define clk_gcc_ufs_ice_core_hw_ctl_clk		0x84e15a5b

#define clk_gcc_ufs_phy_aux_clk			0x17acc8fb

#define clk_gcc_ufs_phy_aux_hw_ctl_clk		0x7dbdb2e2

#define clk_gcc_ufs_rx_symbol_0_clk		0x7f43251c

#define clk_gcc_ufs_rx_symbol_1_clk		0x03182fde

#define clk_gcc_ufs_tx_symbol_0_clk		0x6a9f747a

#define clk_ufs_tx_symbol_0_clk			0xb3fcd0f7

#define clk_ufs_rx_symbol_0_clk			0x17a0f1cd

#define clk_gcc_ufs_unipro_core_clk		0x2daf7fd2

#define clk_gcc_ufs_unipro_core_hw_ctl_clk	0x4a4e0f3d

#define clk_gcc_usb30_master_clk		0xb3b4e2cb

#define clk_gcc_usb30_mock_utmi_clk		0xa800b65a

#define clk_gcc_usb30_sleep_clk			0xd0b65c92