Merge tag 'v4.4.28' into android-4.4.y (c302df26) · Commits · e / devices / android_kernel_sony_msm8998

Documentation/kernel-parameters.txt

+8 −1

Original line number	Diff line number	Diff line
		@@ -1377,7 +1377,14 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
		i8042.nopnp [HW] Don't use ACPIPnP / PnPBIOS to discover KBD/AUX
		controllers
		i8042.notimeout [HW] Ignore timeout condition signalled by controller
		i8042.reset [HW] Reset the controller during init and cleanup
		i8042.reset [HW] Reset the controller during init, cleanup and
		suspend-to-ram transitions, only during s2r
		transitions, or never reset
		Format: { 1 \| Y \| y \| 0 \| N \| n }
		1, Y, y: always reset controller
		0, N, n: don't ever reset controller
		Default: only on s2r transitions on x86; most other
		architectures force reset to be always executed
		i8042.unlock [HW] Unlock (ignore) the keylock
		i8042.kbdreset [HW] Reset device connected to KBD port

Makefile

+1 −1

Original line number	Diff line number	Diff line
		VERSION = 4
		PATCHLEVEL = 4
		SUBLEVEL = 27
		SUBLEVEL = 28
		EXTRAVERSION =
		NAME = Blurry Fish Butt

arch/arc/kernel/signal.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -107,13 +107,13 @@ static int restore_usr_regs(struct pt_regs regs, struct rt_sigframe __user sf)
		struct user_regs_struct uregs;

		err = __copy_from_user(&set, &sf->uc.uc_sigmask, sizeof(set));
		if (!err)
		set_current_blocked(&set);

		err \|= __copy_from_user(&uregs.scratch,
		&(sf->uc.uc_mcontext.regs.scratch),
		sizeof(sf->uc.uc_mcontext.regs.scratch));
		if (err)
		return err;

		set_current_blocked(&set);
		regs->bta = uregs.scratch.bta;
		regs->lp_start = uregs.scratch.lp_start;
		regs->lp_end = uregs.scratch.lp_end;
		@@ -138,7 +138,7 @@ static int restore_usr_regs(struct pt_regs regs, struct rt_sigframe __user sf)
		regs->r0 = uregs.scratch.r0;
		regs->sp = uregs.scratch.sp;

		return err;
		return 0;
		}

		static inline int is_do_ss_needed(unsigned int magic)

arch/arm64/include/asm/percpu.h

+56 −64

Original line number	Diff line number	Diff line
		@@ -44,48 +44,44 @@ static inline unsigned long __percpu_##op(void *ptr, \
		\
		switch (size) { \
		case 1: \
		do { \
		asm ("//__per_cpu_" #op "_1\n" \
		"ldxrb %w[ret], %[ptr]\n" \
		"1: ldxrb %w[ret], %[ptr]\n" \
		#asm_op " %w[ret], %w[ret], %w[val]\n" \
		" stxrb %w[loop], %w[ret], %[ptr]\n" \
		" cbnz %w[loop], 1b" \
		: [loop] "=&r" (loop), [ret] "=&r" (ret), \
		[ptr] "+Q"((u8 )ptr) \
		: [val] "Ir" (val)); \
		} while (loop); \
		break; \
		case 2: \
		do { \
		asm ("//__per_cpu_" #op "_2\n" \
		"ldxrh %w[ret], %[ptr]\n" \
		"1: ldxrh %w[ret], %[ptr]\n" \
		#asm_op " %w[ret], %w[ret], %w[val]\n" \
		" stxrh %w[loop], %w[ret], %[ptr]\n" \
		" cbnz %w[loop], 1b" \
		: [loop] "=&r" (loop), [ret] "=&r" (ret), \
		[ptr] "+Q"((u16 )ptr) \
		: [val] "Ir" (val)); \
		} while (loop); \
		break; \
		case 4: \
		do { \
		asm ("//__per_cpu_" #op "_4\n" \
		"ldxr %w[ret], %[ptr]\n" \
		"1: ldxr %w[ret], %[ptr]\n" \
		#asm_op " %w[ret], %w[ret], %w[val]\n" \
		" stxr %w[loop], %w[ret], %[ptr]\n" \
		" cbnz %w[loop], 1b" \
		: [loop] "=&r" (loop), [ret] "=&r" (ret), \
		[ptr] "+Q"((u32 )ptr) \
		: [val] "Ir" (val)); \
		} while (loop); \
		break; \
		case 8: \
		do { \
		asm ("//__per_cpu_" #op "_8\n" \
		"ldxr %[ret], %[ptr]\n" \
		"1: ldxr %[ret], %[ptr]\n" \
		#asm_op " %[ret], %[ret], %[val]\n" \
		" stxr %w[loop], %[ret], %[ptr]\n" \
		" cbnz %w[loop], 1b" \
		: [loop] "=&r" (loop), [ret] "=&r" (ret), \
		[ptr] "+Q"((u64 )ptr) \
		: [val] "Ir" (val)); \
		} while (loop); \
		break; \
		default: \
		BUILD_BUG(); \
		@@ -150,44 +146,40 @@ static inline unsigned long __percpu_xchg(void *ptr, unsigned long val,

		switch (size) {
		case 1:
		do {
		asm ("//__percpu_xchg_1\n"
		"ldxrb %w[ret], %[ptr]\n"
		"1: ldxrb %w[ret], %[ptr]\n"
		" stxrb %w[loop], %w[val], %[ptr]\n"
		" cbnz %w[loop], 1b"
		: [loop] "=&r"(loop), [ret] "=&r"(ret),
		[ptr] "+Q"((u8 )ptr)
		: [val] "r" (val));
		} while (loop);
		break;
		case 2:
		do {
		asm ("//__percpu_xchg_2\n"
		"ldxrh %w[ret], %[ptr]\n"
		"1: ldxrh %w[ret], %[ptr]\n"
		" stxrh %w[loop], %w[val], %[ptr]\n"
		" cbnz %w[loop], 1b"
		: [loop] "=&r"(loop), [ret] "=&r"(ret),
		[ptr] "+Q"((u16 )ptr)
		: [val] "r" (val));
		} while (loop);
		break;
		case 4:
		do {
		asm ("//__percpu_xchg_4\n"
		"ldxr %w[ret], %[ptr]\n"
		"1: ldxr %w[ret], %[ptr]\n"
		" stxr %w[loop], %w[val], %[ptr]\n"
		" cbnz %w[loop], 1b"
		: [loop] "=&r"(loop), [ret] "=&r"(ret),
		[ptr] "+Q"((u32 )ptr)
		: [val] "r" (val));
		} while (loop);
		break;
		case 8:
		do {
		asm ("//__percpu_xchg_8\n"
		"ldxr %[ret], %[ptr]\n"
		"1: ldxr %[ret], %[ptr]\n"
		" stxr %w[loop], %[val], %[ptr]\n"
		" cbnz %w[loop], 1b"
		: [loop] "=&r"(loop), [ret] "=&r"(ret),
		[ptr] "+Q"((u64 )ptr)
		: [val] "r" (val));
		} while (loop);
		break;
		default:
		BUILD_BUG();

arch/arm64/kernel/head.S

+2 −1

Original line number	Diff line number	Diff line
		@@ -592,8 +592,9 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
		b.lt 4f // Skip if no PMU present
		mrs x0, pmcr_el0 // Disable debug access traps
		ubfx x0, x0, #11, #5 // to EL2 and allow access to
		msr mdcr_el2, x0 // all PMU counters from EL1
		4:
		csel x0, xzr, x0, lt // all PMU counters from EL1
		msr mdcr_el2, x0 // (if they exist)

		/* Stage-2 translation */
		msr vttbr_el2, xzr