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Commit c30184d9 authored Aug 10, 2017 by Will Deacon Committed by Greg Hackmann Jan 18, 2018

FROMLIST: arm64: mm: Rename post_ttbr0_update_workaround



The post_ttbr0_update_workaround hook applies to any change to TTBRx_EL1.
Since we're using TTBR1 for the ASID, rename the hook to make it clearer
as to what it's doing.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Tested-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git


 commit 158d495899ce55db453f682a8ac8390d5a426578)

Change-Id: Iaf152ca1bd0a20bd15a77afac4ad4e9ea8ada08f
Signed-off-by: Greg Hackmann <ghackmann@google.com>

parent ca0ebb4e

arch/arm64/include/asm/assembler.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -399,9 +399,9 @@ alternative_endif
		.endm

		/*
		* Errata workaround post TTBR0_EL1 update.
		* Errata workaround post TTBRx_EL1 update.
		*/
		.macro post_ttbr0_update_workaround
		.macro post_ttbr_update_workaround
		#ifdef CONFIG_CAVIUM_ERRATUM_27456
		alternative_if ARM64_WORKAROUND_CAVIUM_27456
		ic iallu

arch/arm64/kernel/entry.S

+1 −1

Original line number	Diff line number	Diff line
		@@ -241,7 +241,7 @@ alternative_else_nop_endif
		* Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
		* corruption).
		*/
		post_ttbr0_update_workaround
		post_ttbr_update_workaround
		.endif
		1:
		.if \el != 0

arch/arm64/mm/proc.S

+1 −1

Original line number	Diff line number	Diff line
		@@ -145,7 +145,7 @@ ENTRY(cpu_do_switch_mm)
		isb
		msr ttbr0_el1, x0 // now update TTBR0
		isb
		post_ttbr0_update_workaround
		post_ttbr_update_workaround
		ret
		ENDPROC(cpu_do_switch_mm)