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Commit c25dba2a authored by Sachin Bhayare's avatar Sachin Bhayare Committed by Gerrit - the friendly Code Review server
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msm: mdss: add support for mdss throttle clock handling 



Update mdss throttle clock status based on status of display.

Change-Id: Ife21df0c570240c075f039b8d49514bb323021da
Signed-off-by: default avatarSachin Bhayare <sachin.bhayare@codeaurora.org>
parent 5d78c03a

drivers/video/fbdev/msm/mdss.h

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ enum mdss_mdp_clk_type { 
	MDSS_CLK_MDP_LUT,

	MDSS_CLK_MDP_VSYNC,

	MDSS_CLK_MNOC_AHB,

	MDSS_CLK_THROTTLE_AXI,

	MDSS_MAX_CLK

};

drivers/video/fbdev/msm/mdss_mdp.c

+9 −2
Original line number Diff line number Diff line
@@ -1373,7 +1373,9 @@ static inline void __mdss_mdp_reg_access_clk_enable( 
		mdss_mdp_clk_update(MDSS_CLK_AHB, 1);

		mdss_mdp_clk_update(MDSS_CLK_AXI, 1);

		mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, 1);

		mdss_mdp_clk_update(MDSS_CLK_THROTTLE_AXI, 1);

	} else {

		mdss_mdp_clk_update(MDSS_CLK_THROTTLE_AXI, 0);

		mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, 0);

		mdss_mdp_clk_update(MDSS_CLK_AXI, 0);

		mdss_mdp_clk_update(MDSS_CLK_AHB, 0);
@@ -1415,6 +1417,7 @@ static void __mdss_mdp_clk_control(struct mdss_data_type *mdata, bool enable) 
		mdss_mdp_clk_update(MDSS_CLK_AXI, 1);

		mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, 1);

		mdss_mdp_clk_update(MDSS_CLK_MDP_LUT, 1);

		mdss_mdp_clk_update(MDSS_CLK_THROTTLE_AXI, 1);

		if (mdata->vsync_ena)

			mdss_mdp_clk_update(MDSS_CLK_MDP_VSYNC, 1);

	} else {
@@ -1430,6 +1433,7 @@ static void __mdss_mdp_clk_control(struct mdss_data_type *mdata, bool enable) 
		mdss_mdp_clk_update(MDSS_CLK_AXI, 0);

		mdss_mdp_clk_update(MDSS_CLK_AHB, 0);

		mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, 0);

		mdss_mdp_clk_update(MDSS_CLK_THROTTLE_AXI, 0);



		/* release iommu control */

		mdss_iommu_ctrl(0);
@@ -1915,8 +1919,7 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata) 


	if (mdss_mdp_irq_clk_register(mdata, "bus_clk", MDSS_CLK_AXI) ||

	    mdss_mdp_irq_clk_register(mdata, "iface_clk", MDSS_CLK_AHB) ||

	    mdss_mdp_irq_clk_register(mdata, "core_clk",

				      MDSS_CLK_MDP_CORE))

	    mdss_mdp_irq_clk_register(mdata, "core_clk", MDSS_CLK_MDP_CORE))

		return -EINVAL;



	/* lut_clk is not present on all MDSS revisions */
@@ -1928,6 +1931,10 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata) 
	/* this clk is not present on all MDSS revisions */

	mdss_mdp_irq_clk_register(mdata, "mnoc_clk", MDSS_CLK_MNOC_AHB);



	/* this clk is not present on all MDSS revisions */

	mdss_mdp_irq_clk_register(mdata, "throttle_bus_clk",

				  MDSS_CLK_THROTTLE_AXI);



	/* Setting the default clock rate to the max supported.*/

	mdss_mdp_set_clk_rate(mdata->max_mdp_clk_rate, false);

	pr_debug("mdp clk rate=%ld\n",