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Commit c1cd824a authored by Ingrid Gallardo's avatar Ingrid Gallardo Committed by Jeykumar Sankaran
Browse files

msm: mdss: update QoS settings for concurrent writeback 



Update the QoS settings for concurrent writeback in the
supported targets.

Change-Id: I9f190393eb4fcf9f5b3e004732cafeb7ee622894
Signed-off-by: default avatarIngrid Gallardo <ingridg@codeaurora.org>
parent 626caf4e

drivers/video/fbdev/msm/mdss.h

+1 −0
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ enum mdss_qos_settings { 
	MDSS_QOS_REMAPPER,

	MDSS_QOS_IB_NOCR,

	MDSS_QOS_WB2_WRITE_GATHER_EN,

	MDSS_QOS_WB_QOS,

	MDSS_QOS_MAX,

};

drivers/video/fbdev/msm/mdss_mdp.c

+2 −0
Original line number Diff line number Diff line
@@ -1992,6 +1992,8 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) 


		set_bit(MDSS_QOS_PER_PIPE_IB, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_REMAPPER, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_TS_PREFILL, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_WB_QOS, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_OVERHEAD_FACTOR, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_CDP, mdata->mdss_qos_map); /* cdp supported */

		mdata->enable_cdp = false; /* disable cdp */

drivers/video/fbdev/msm/mdss_mdp.h

+5 −0
Original line number Diff line number Diff line
@@ -122,6 +122,11 @@ 
 */

#define MDSS_MDP_DS_OVERFETCH_SIZE 5



#define QOS_LUT_NRT_READ	0x0

#define QOS_LUT_CWB_READ	0xe4000000

#define PANIC_LUT_NRT_READ	0x0

#define ROBUST_LUT_NRT_READ	0xFFFF



/* hw cursor can only be setup in highest mixer stage */

#define HW_CURSOR_STAGE(mdata) \

	(((mdata)->max_target_zorder + MDSS_MDP_STAGE_0) - 1)

drivers/video/fbdev/msm/mdss_mdp_hwio.h

+4 −0
Original line number Diff line number Diff line
@@ -541,6 +541,10 @@ enum mdss_mdp_writeback_index { 
#define MDSS_MDP_REG_WB_N16_INIT_PHASE_Y_C12		0x06C

#define MDSS_MDP_REG_WB_OUT_SIZE			0x074

#define MDSS_MDP_REG_WB_ALPHA_X_VALUE			0x078

#define MDSS_MDP_REG_WB_DANGER_LUT			0x084

#define MDSS_MDP_REG_WB_SAFE_LUT			0x088

#define MDSS_MDP_REG_WB_CREQ_LUT			0x08c

#define MDSS_MDP_REG_WB_QOS_CTRL			0x090

#define MDSS_MDP_REG_WB_CSC_BASE			0x260

#define MDSS_MDP_REG_WB_DST_ADDR_SW_STATUS		0x2B0

#define MDSS_MDP_REG_WB_CDP_CTRL			0x2B4

drivers/video/fbdev/msm/mdss_mdp_intf_writeback.c

+28 −0
Original line number Diff line number Diff line
@@ -124,6 +124,30 @@ static inline void mdp_wb_write(struct mdss_mdp_writeback_ctx *ctx, 
	writel_relaxed(val, ctx->base + reg);

}



static void mdss_mdp_set_qos_wb(struct mdss_mdp_ctl *ctl,

	struct mdss_mdp_writeback_ctx *ctx)

{

	u32 wb_qos_setup = QOS_LUT_NRT_READ;

	struct mdss_mdp_cwb *cwb = NULL;

	struct mdss_overlay_private *mdp5_data;

	struct mdss_data_type *mdata = mdss_mdp_get_mdata();



	if (false == test_bit(MDSS_QOS_WB_QOS, mdata->mdss_qos_map))

		return;



	mdp5_data = mfd_to_mdp5_data(ctl->mfd);

	cwb = &mdp5_data->cwb;



	if (cwb->valid)

		wb_qos_setup = QOS_LUT_CWB_READ;

	else

		wb_qos_setup = QOS_LUT_NRT_READ;



	mdp_wb_write(ctx, MDSS_MDP_REG_WB_DANGER_LUT, PANIC_LUT_NRT_READ);

	mdp_wb_write(ctx, MDSS_MDP_REG_WB_SAFE_LUT, ROBUST_LUT_NRT_READ);

	mdp_wb_write(ctx, MDSS_MDP_REG_WB_CREQ_LUT, wb_qos_setup);

}



static void mdss_mdp_set_ot_limit_wb(struct mdss_mdp_writeback_ctx *ctx,

					int is_wfd)

{
@@ -495,6 +519,8 @@ int mdss_mdp_writeback_prepare_cwb(struct mdss_mdp_ctl *ctl, 
	if (ctl->mdata->default_ot_wr_limit || ctl->mdata->default_ot_rd_limit)

		mdss_mdp_set_ot_limit_wb(ctx, false);



	mdss_mdp_set_qos_wb(ctl, ctx);



	return ret;

}
@@ -897,6 +923,8 @@ static int mdss_mdp_writeback_display(struct mdss_mdp_ctl *ctl, void *arg) 
			ctl->mdata->default_ot_rd_limit)

		mdss_mdp_set_ot_limit_wb(ctx, true);



	mdss_mdp_set_qos_wb(ctl, ctx);



	wb_args = (struct mdss_mdp_writeback_arg *) arg;

	if (!wb_args)

		return -ENOENT;