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Commit bf99dc3b authored by Suprith Malligere Shankaregowda's avatar Suprith Malligere Shankaregowda Committed by Gerrit - the friendly Code Review server
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drm: msm: sde: Fix SMMU fault during DRM test 



This change is done to detach all pipes first before the first commit
proceed, Kernel will have to do the pipe detach when kernel got the first
valid frame and we want to detach all the splash pipes after the LK is
being notified to stop.

Change-Id: I3a599a102286596333a35273e27d8a363f2134b7
Signed-off-by: default avatarSuprith Malligere Shankaregowda <supgow@codeaurora.org>
parent 7b270ed1

drivers/gpu/drm/msm/sde/sde_splash.c

+53 −1
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include "sde_rm.h"

#include "dsi_display.h"

#include "sde_hdmi.h"

#include "sde_crtc.h"



#define MDP_SSPP_TOP0_OFF		0x1000

#define DISP_INTF_SEL			0x004
@@ -878,12 +879,61 @@ int sde_splash_free_resource(struct msm_kms *kms, 
	return ret;

}



/*

 * Below function will detach all the pipes of the mixer

 */

static int _sde_splash_clear_mixer_blendstage(struct msm_kms *kms,

				struct drm_atomic_state *state)

{

	struct drm_crtc *crtc;

	struct sde_crtc *sde_crtc;

	struct sde_crtc_mixer *mixer;

	int i;

	struct sde_splash_info *sinfo;

	struct sde_kms *sde_kms = to_sde_kms(kms);



	sinfo = &sde_kms->splash_info;



	if (!sinfo) {

		SDE_ERROR("%s(%d): invalid splash info\n", __func__, __LINE__);

		return -EINVAL;

	}



	for (i = 0; i < state->dev->mode_config.num_crtc; i++) {

		crtc = state->crtcs[i];

		if (!crtc) {

			SDE_ERROR("CRTC is NULL");

			continue;

		}

		sde_crtc = to_sde_crtc(crtc);

		if (!sde_crtc) {

			SDE_ERROR("SDE CRTC is NULL");

			return -EINVAL;

		}

		mixer = sde_crtc->mixers;

		if (!mixer) {

			SDE_ERROR("Mixer is NULL");

			return -EINVAL;

		}

		for (i = 0; i < sde_crtc->num_mixers; i++) {

			if (mixer[i].hw_ctl->ops.clear_all_blendstages)

				mixer[i].hw_ctl->ops.clear_all_blendstages(

						mixer[i].hw_ctl,

						sinfo->handoff,

						sinfo->reserved_pipe_info,

						MAX_BLOCKS);

		}

	}

	return 0;

}



/*

 * Below function will notify LK to stop display splash.

 */

int sde_splash_lk_stop_splash(struct msm_kms *kms,

				struct drm_atomic_state *state)

{

	int error = 0;

	struct sde_splash_info *sinfo;

	struct sde_kms *sde_kms = to_sde_kms(kms);
@@ -902,8 +952,10 @@ int sde_splash_lk_stop_splash(struct msm_kms *kms, 
			_sde_splash_notify_lk_stop_splash(sde_kms->hw_intr);



		sinfo->display_splash_enabled = false;



		error = _sde_splash_clear_mixer_blendstage(kms, state);

	}

	mutex_unlock(&sde_splash_lock);



	return 0;

	return error;

}