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Commit bde75567 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'samsung/cleanup-exynos-clock' into next/soc 



Conflicts:
	arch/arm/mach-exynos/clock-exynos4.c
	arch/arm/mach-exynos/clock.c

The cleanup moves the exynos4 clock implementation away, while
the other branch modifies the file with the old name.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 62a16d02 44b2cef5

arch/arm/mach-exynos/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -12,7 +12,8 @@ obj- := 


# Core



obj-$(CONFIG_ARCH_EXYNOS4)	+= common.o clock.o

obj-$(CONFIG_ARCH_EXYNOS)	+= common.o

obj-$(CONFIG_ARCH_EXYNOS4)	+= clock-exynos4.o

obj-$(CONFIG_CPU_EXYNOS4210)	+= clock-exynos4210.o

obj-$(CONFIG_SOC_EXYNOS4212)	+= clock-exynos4212.o

arch/arm/mach-exynos/clock.c→arch/arm/mach-exynos/clock-exynos4.c

+1568 −0

File changed and moved.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-exynos/include/mach/exynos4-clock.h→arch/arm/mach-exynos/clock-exynos4.h

+30 −0
Original line number Diff line number Diff line 
/*

 * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * Header file for exynos4 clock support
@@ -16,25 +14,14 @@ 


#include <linux/clk.h>



extern struct clk clk_sclk_hdmi27m;

extern struct clk clk_sclk_usbphy0;

extern struct clk clk_sclk_usbphy1;

extern struct clk clk_sclk_hdmiphy;



extern struct clksrc_clk clk_sclk_apll;

extern struct clksrc_clk clk_mout_mpll;

extern struct clksrc_clk clk_aclk_133;

extern struct clksrc_clk clk_mout_epll;

extern struct clksrc_clk clk_sclk_vpll;



extern struct clk *clkset_corebus_list[];

extern struct clksrc_sources clkset_mout_corebus;

extern struct clksrc_clk exynos4_clk_aclk_133;

extern struct clksrc_clk exynos4_clk_mout_mpll;



extern struct clk *clkset_aclk_top_list[];

extern struct clksrc_sources clkset_aclk;

extern struct clksrc_sources exynos4_clkset_mout_corebus;

extern struct clksrc_sources exynos4_clkset_group;



extern struct clk *clkset_group_list[];

extern struct clksrc_sources clkset_group;

extern struct clk *exynos4_clkset_aclk_top_list[];

extern struct clk *exynos4_clkset_group_list[];



extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);

extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);

arch/arm/mach-exynos/clock-exynos4210.c

+23 −25
Original line number Diff line number Diff line 
/*

 * linux/arch/arm/mach-exynos4/clock-exynos4210.c

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * EXYNOS4210 - Clock support
@@ -28,20 +26,20 @@ 
#include <mach/hardware.h>

#include <mach/map.h>

#include <mach/regs-clock.h>

#include <mach/exynos4-clock.h>



#include "common.h"

#include "clock-exynos4.h"



#ifdef CONFIG_PM_SLEEP

static struct sleep_save exynos4210_clock_save[] = {

	SAVE_ITEM(S5P_CLKSRC_IMAGE),

	SAVE_ITEM(S5P_CLKSRC_LCD1),

	SAVE_ITEM(S5P_CLKDIV_IMAGE),

	SAVE_ITEM(S5P_CLKDIV_LCD1),

	SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),

	SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),

	SAVE_ITEM(S5P_CLKGATE_IP_LCD1),

	SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),

	SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),

	SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),

	SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),

	SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),

	SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),

	SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),

	SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),

	SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),

};

#endif
@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = { 


static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);

	return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);

}



static struct clksrc_clk clksrcs[] = {
@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = { 
			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 24),

		},

		.sources = &clkset_mout_corebus,

		.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },

		.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },

		.sources = &exynos4_clkset_mout_corebus,

		.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },

		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },

	}, {

		.clk		= {

			.name		= "sclk_fimd",
@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = { 
			.enable		= exynos4_clksrc_mask_lcd1_ctrl,

			.ctrlbit	= (1 << 0),

		},

		.sources = &clkset_group,

		.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },

		.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },

		.sources = &exynos4_clkset_group,

		.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },

		.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },

	},

};
@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = { 
	{

		.name		= "sataphy",

		.id		= -1,

		.parent		= &clk_aclk_133.clk,

		.parent		= &exynos4_clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 3),

	}, {

		.name		= "sata",

		.id		= -1,

		.parent		= &clk_aclk_133.clk,

		.parent		= &exynos4_clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 10),

	}, {
@@ -117,7 +115,7 @@ static void exynos4210_clock_resume(void) 
#define exynos4210_clock_resume NULL

#endif



struct syscore_ops exynos4210_clock_syscore_ops = {

static struct syscore_ops exynos4210_clock_syscore_ops = {

	.suspend	= exynos4210_clock_suspend,

	.resume		= exynos4210_clock_resume,

};
@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void) 
{

	int ptr;



	clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;

	clk_mout_mpll.reg_src.shift = 8;

	clk_mout_mpll.reg_src.size = 1;

	exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;

	exynos4_clk_mout_mpll.reg_src.shift = 8;

	exynos4_clk_mout_mpll.reg_src.size = 1;



	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)

		s3c_register_clksrc(sysclks[ptr], 1);

arch/arm/mach-exynos/clock-exynos4212.c

+15 −17
Original line number Diff line number Diff line 
/*

 * linux/arch/arm/mach-exynos4/clock-exynos4212.c

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * EXYNOS4212 - Clock support
@@ -28,22 +26,22 @@ 
#include <mach/hardware.h>

#include <mach/map.h>

#include <mach/regs-clock.h>

#include <mach/exynos4-clock.h>



#include "common.h"

#include "clock-exynos4.h"



#ifdef CONFIG_PM_SLEEP

static struct sleep_save exynos4212_clock_save[] = {

	SAVE_ITEM(S5P_CLKSRC_IMAGE),

	SAVE_ITEM(S5P_CLKDIV_IMAGE),

	SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),

	SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),

	SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),

	SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),

	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),

	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),

};

#endif



static struct clk *clk_src_mpll_user_list[] = {

	[0] = &clk_fin_mpll,

	[1] = &clk_mout_mpll.clk,

	[1] = &exynos4_clk_mout_mpll.clk,

};



static struct clksrc_sources clk_src_mpll_user = {
@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = { 
		.name		= "mout_mpll_user",

	},

	.sources	= &clk_src_mpll_user,

	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },

	.reg_src	= { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },

};



static struct clksrc_clk *sysclks[] = {
@@ -89,7 +87,7 @@ static void exynos4212_clock_resume(void) 
#define exynos4212_clock_resume NULL

#endif



struct syscore_ops exynos4212_clock_syscore_ops = {

static struct syscore_ops exynos4212_clock_syscore_ops = {

	.suspend	= exynos4212_clock_suspend,

	.resume		= exynos4212_clock_resume,

};
@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void) 
	int ptr;



	/* usbphy1 is removed */

	clkset_group_list[4] = NULL;

	exynos4_clkset_group_list[4] = NULL;



	/* mout_mpll_user is used */

	clkset_group_list[6] = &clk_mout_mpll_user.clk;

	clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;

	exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;

	exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;



	clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;

	clk_mout_mpll.reg_src.shift = 12;

	clk_mout_mpll.reg_src.size = 1;

	exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;

	exynos4_clk_mout_mpll.reg_src.shift = 12;

	exynos4_clk_mout_mpll.reg_src.size = 1;



	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)

		s3c_register_clksrc(sysclks[ptr], 1);