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Commit ba948911 authored by Narender Ankam's avatar Narender Ankam Committed by Gerrit - the friendly Code Review server
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msm: mdss: dp: fix div by zero error 



If for some reasons like ioctl fuss test or reading dpcd caps failed,
max lane count supported might be zero. In such cases handle link clk
calculation gracefully.

Change-Id: I7cb08abce76025930681f6532c03708793d3acc4
Signed-off-by: default avatarNarender Ankam <nankam@codeaurora.org>
parent 90076dbf

drivers/video/fbdev/msm/mdss_dp.c

+1 −0
Original line number Diff line number Diff line
@@ -1637,6 +1637,7 @@ int mdss_dp_on_hpd(struct mdss_dp_drv_pdata *dp_drv) 
	dp_drv->link_rate = mdss_dp_gen_link_clk(dp_drv);

	if (!dp_drv->link_rate) {

		pr_err("Unable to configure required link rate\n");

		mdss_dp_clk_ctrl(dp_drv, DP_CORE_PM, false);

		ret = -EINVAL;

		goto exit;

	}

drivers/video/fbdev/msm/mdss_dp_aux.c

+5 −0
Original line number Diff line number Diff line
@@ -684,6 +684,11 @@ char mdss_dp_gen_link_clk(struct mdss_dp_drv_pdata *dp) 
	pr_debug("clk_rate=%llu, bpp= %d, lane_cnt=%d\n",

	       pinfo->clk_rate, pinfo->bpp, lane_cnt);



	if (lane_cnt == 0) {

		pr_warn("Invalid max lane count\n");

		return 0;

	}



	/*

	 * The max pixel clock supported is 675Mhz. The

	 * current calculations below will make sure