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Commit b97a5e56 authored by Dhaval Patel's avatar Dhaval Patel Committed by Gerrit - the friendly Code Review server
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drm/sde: move hardware catalog to dtsi parser 



Current SDE DRM driver uses hardcoded structures
for target catalog information. This patch
removes the hardcoding from software and moves
it to dtsi parsing. It helps to remove the target
specific code drm directory and keep it in dtsi.

Change-Id: I2effaf65d7af5e22714c6e61e7f76a7e24ff86d9
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent f02f23f1

Documentation/devicetree/bindings/display/msm/sde.txt

+226 −2
Original line number Diff line number Diff line
@@ -18,6 +18,51 @@ Required properties 
- interrupt-controller: Mark the device node as an interrupt controller.

- #interrupt-cells: Should be one. The first cell is interrupt number.

- iommus: Specifies the SID's used by this context bank.

- qcom,sde-sspp-type:		Array of strings for SDE source surface pipes type information.

				A source pipe can be "vig", "rgb", "dma" or "cursor" type.

				Number of xin ids defined should match the number of offsets

				defined in property: qcom,sde-sspp-off.

- qcom,sde-sspp-off:		Array of offset for SDE source surface pipes. The offsets

				are calculated from register "mdp_phys" defined in

				reg property + "sde-off". The number of offsets defined here should

				reflect the amount of pipes that can be active in SDE for

				this configuration.

- qcom,sde-sspp-xin-id:		Array of VBIF clients ids (xins) corresponding

				to the respective source pipes. Number of xin ids

				defined should match the number of offsets

				defined in property: qcom,sde-sspp-off.

- qcom,sde-ctl-off:		Array of offset addresses for the available ctl

				hw blocks within SDE, these offsets are

				calculated from register "mdp_phys" defined in

				reg property.  The number of ctl offsets defined

				here should reflect the number of control paths

				that can be configured concurrently on SDE for

				this configuration.

- qcom,sde-wb-off:		Array of offset addresses for the programmable

				writeback blocks within SDE.

- qcom,sde-wb-xin-id:		Array of VBIF clients ids (xins) corresponding

				to the respective writeback. Number of xin ids

				defined should match the number of offsets

				defined in property: qcom,sde-wb-off.

- qcom,sde-mixer-off:	 	Array of offset addresses for the available

				mixer blocks that can drive data to panel

				interfaces. These offsets are be calculated from

				register "mdp_phys" defined in reg property.

				The number of offsets defined should reflect the

				amount of mixers that can drive data to a panel

				interface.

- qcom,sde-dspp-off: 		Array of offset addresses for the available dspp

				blocks. These offsets are calculated from

				register "mdp_phys" defined in reg property.

- qcom,sde-pp-off:		Array of offset addresses for the available

				pingpong blocks. These offsets are calculated

				from register "mdp_phys" defined in reg property.

- qcom,sde-intf-off:		Array of offset addresses for the available SDE

				interface blocks that can drive data to a

				panel controller. The offsets are calculated

				from "mdp_phys" defined in reg property. The number

				of offsets defined should reflect the number of

				programmable interface blocks available in hardware.



Optional properties:

- clock-rate:		List of clock rates in Hz.
@@ -39,11 +84,99 @@ Optional properties: 
				-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off

- qcom,sde-reg-bus:		Property to provide Bus scaling for register access for

				mdss blocks.



- qcom,sde-sspp-src-size:	A u32 value indicates the address range for each sspp.

- qcom,sde-mixer-size:		A u32 value indicates the address range for each mixer.

- qcom,sde-ctl-size:		A u32 value indicates the address range for each ctl.

- qcom,sde-dspp-size:		A u32 value indicates the address range for each dspp.

- qcom,sde-intf-size:		A u32 value indicates the address range for each intf.

- qcom,sde-dsc-size:		A u32 value indicates the address range for each dsc.

- qcom,sde-cdm-size:		A u32 value indicates the address range for each cdm.

- qcom,sde-pp-size:		A u32 value indicates the address range for each pingpong.

- qcom,sde-wb-size:		A u32 value indicates the address range for each writeback.

- qcom,sde-len:			A u32 entry for SDE address range.

- qcom,sde-intf-max-prefetch-lines:	Array of u32 values for max prefetch lines on

				each interface.

- qcom,sde-sspp-linewidth:	A u32 value indicates the max sspp line width.

- qcom,sde-mixer-linewidth:	A u32 value indicates the max mixer line width.

- qcom,sde-wb-linewidth:	A u32 value indicates the max writeback line width.

- qcom,sde-sspp-scale-size:	A u32 value indicates the scaling block size on sspp.

- qcom,sde-mixer-blendstages:	A u32 value indicates the max mixer blend stages for

				alpha blending.

- qcom,sde-qseed-type:		A string entry indiates qseed support on sspp and wb.

				It supports "qssedv3" and "qseedv2" entries for qseed

				type. By default "qseedv2" is used if this optional property

				is not defined.

- qcom,sde-highest-bank-bit:	A u32 property to indicate GPU/Camera/Video highest memory

				bank bit used for tile format buffers.

- qcom,sde-panic-per-pipe:	Boolean property to indicate if panic signal

				control feature is available on each source pipe.

- qcom,sde-has-src-split:	Boolean property to indicate if source split

				feature is available or not.

- qcom,sde-has-mixer-gc:	Boolean property to indicate if mixer has gamma correction

				feature available or not.

- qcom,sde-has-cdp:		Boolean property to indicate if cdp feature is

				available or not.

- qcom,sde-sspp-clk-ctrl:	Array of offsets describing clk control

				offsets for dynamic clock gating. 1st value

				in the array represents offset of the control

				register. 2nd value represents bit offset within

				control register. Number of offsets defined should

				match the number of offsets defined in

				property: qcom,sde-sspp-off

- qcom,sde-sspp-clk-status:	Array of offsets describing clk status

				offsets for dynamic clock gating. 1st value

				in the array represents offset of the status

				register. 2nd value represents bit offset within

				control register. Number of offsets defined should

				match the number of offsets defined in

				property: qcom,sde-sspp-off.

- qcom,sde-sspp-danger-lut:	Array of u32 values indicating the danger luts on each

				sspp. Number of offsets defined should

				match the number of offsets defined in

				property: qcom,sde-sspp-off.

- qcom,sde-sspp-safe-lut:	Array of u32 values indicating the safe luts on each

				sspp. Number of offsets defined should

				match the number of offsets defined in

				property: qcom,sde-sspp-off.

- qcom,sde-sspp-qseed-off:	A u32 offset value indicates the qseed block offset

				from sspp base. It will install qseed property on

				vig and rgb sspp pipes.

- qcom,sde-sspp-csc-off:	A u32 offset value indicates the csc block offset

				from sspp base. It will be used to install the csc

				property on vig type pipe.

- qcom,sde-sspp-max-rects:	Array of u32 values indicating maximum rectangles supported

				on each sspp. This property is for multirect feature support.

				Number of offsets defined should match the number of

				offsets defined in property: qcom,sde-sspp-off.

- qcom,sde-intf-type:		Array of string provides the interface type information.

				Possible string values

					"dsi" - dsi display interface

					"dp" - Display Port interface

					"hdmi" - HDMI display interface

				An interface is considered as "none" if interface type

				is not defined.

- qcom,sde-off:			SDE offset from "mdp_phys" defined in reg property.

- qcom,sde-cdm-off:	 	Array of offset addresses for the available

				cdm blocks. These offsets will be calculated from

				register "mdp_phys" defined in reg property.

- qcom,sde-te-off:		A u32 offset indicates the te block offset on pingpong.

				This offset is 0x0 by default.

- qcom,sde-te2-off:		A u32 offset indicates the te2 block offset on pingpong.

- qcom,sde-te-size:		A u32 value indicates the te block address range.

- qcom,sde-te2-size:		A u32 value indicates the te2 block address range.

- qcom,sde-dsc-off:	 	A u32 offset indicates the dsc block offset on pingpong.

- qcom,sde-dspp-igc-off:	A u32 offset indicates the igc block offset on dssp.

- qcom,sde-dspp-pcc-off:	A u32 offset indicates the pcc block offset on dssp.

- qcom,sde-dspp-gc-off:		A u32 offset indicates the gc block offset on dssp.

- qcom,sde-dspp-pa-off:		A u32 offset indicates the pa block offset on dssp.

- qcom,sde-dspp-gamut-off:	A u32 offset indicates the gamut block offset on dssp.

- qcom,sde-dspp-dither-off:	A u32 offset indicates the dither block offset on dssp.

- qcom,sde-dspp-hist-off:	A u32 offset indicates the hist block offset on dssp.

- qcom,sde-dspp-ad-off:		A u32 offset indicates the ad block offset on dssp.



Bus Scaling Data:

- qcom,msm-bus,name:		String property describing client name.

- qcom,msm-bus,num-cases:	This is the the number of Bus Scaling use cases

- qcom,msm-bus,num-cases:	This is the number of Bus Scaling use cases

				defined in the vectors property.

- qcom,msm-bus,num-paths:	This represents the number of paths in each

				Bus Scaling Usecase.
@@ -90,6 +223,97 @@ Example: 
    #interrupt-cells = <1>;

    iommus = <&mdp_smmu 0>;



    qcom,sde-off = <0x1000>;

    qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400

		     0x00002600 0x00002800>;

    qcom,sde-mixer-off = <0x00045000 0x00046000

			0x00047000 0x0004a000>;

    qcom,sde-dspp-off = <0x00055000 0x00057000>;

    qcom,sde-wb-off = <0x00066000>;

    qcom,sde-wb-xin-id = <6>;

    qcom,sde-intf-off = <0x0006b000 0x0006b800

			0x0006c000 0x0006c800>;

    qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi";

    qcom,sde-pp-off = <0x00071000 0x00071800

			  0x00072000 0x00072800>;

    qcom,sde-cdm-off = <0x0007a200>;

    qcom,sde-dsc-off = <0x00081000 0x00081400>;

    qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;



    qcom,sde-sspp-type = "vig", "vig", "vig",

			      "vig", "rgb", "rgb",

			      "rgb", "rgb", "dma",

			      "dma", "cursor", "cursor";



    qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000

		      0x0000b000 0x00015000 0x00017000

		      0x00019000 0x0001b000 0x00025000

		      0x00027000 0x00035000 0x00037000>;



    qcom,sde-sspp-xin-id = <0 4 8

			12 1 5

			9 13 2

			10 7 7>;



    /* offsets are relative to "mdp_phys + qcom,sde-off */

    qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,

			  <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,

			  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,

			  <0x3b0 16>;

    qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,

			  <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,

			  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,

			  <0x3b0 16>;

    qcom,sde-mixer-linewidth = <2560>;

    qcom,sde-sspp-linewidth = <2560>;

    qcom,sde-mixer-blendstages = <0x7>;

    qcom,sde-highest-bank-bit = <0x2>;

    qcom,sde-panic-per-pipe;

    qcom,sde-has-cdp;

    qcom,sde-has-src-split;

    qcom,sde-sspp-src-size = <0x100>;

    qcom,sde-mixer-size = <0x100>;

    qcom,sde-ctl-size = <0x100>;

    qcom,sde-dspp-size = <0x100>;

    qcom,sde-intf-size = <0x100>;

    qcom,sde-dsc-size = <0x100>;

    qcom,sde-cdm-size = <0x100>;

    qcom,sde-pp-size = <0x100>;

    qcom,sde-wb-size = <0x100>;

    qcom,sde-len = <0x100>;

    qcom,sde-wb-linewidth = <2560>;

    qcom,sde-sspp-scale-size = <0x100>;

    qcom,sde-mixer-blendstages = <0x8>;

    qcom,sde-qseed-type = "qseedv2";

    qcom,sde-highest-bank-bit = <15>;

    qcom,sde-has-mixer-gc;

    qcom,sde-sspp-danger-lut = <0x55 0x55 0x55 0x55

				0x55 0x55 0x55 0x55

				0xaa 0xaa

				0xbb 0xbb>;

    qcom,sde-sspp-safe-lut = <0x11 0x11 0x11 0x11

				0x11 0x11 0x11 0x11

				0xaa 0xaa

				0xbb 0xbb>;

    qcom,sde-sspp-max-rects = <1 1 1 1

				1 1 1 1

				1 1

				1 1>;

    qcom,sde-te-off = <0x100>;

    qcom,sde-te2-off = <0x100>;

    qcom,sde-te-size = <0xffff>;

    qcom,sde-te2-size = <0xffff>;

    qcom,sde-sspp-qseed-off = <0x100>;

    qcom,sde-sspp-csc-off = <0x100>;

    qcom,sde-dspp-igc-off = <0x100>;

    qcom,sde-dspp-pcc-off = <0x100>;

    qcom,sde-dspp-gc-off = <0x100>;

    qcom,sde-dspp-pa-off = <0x100>;

    qcom,sde-dspp-gamut-off = <0x100>;

    qcom,sde-dspp-dither-off = <0x100>;

    qcom,sde-dspp-hist-off = <0x100>;

    qcom,sde-dspp-ad-off = <0x100>;



    qcom,platform-supply-entries {

       #address-cells = <1>;

       #size-cells = <0>;

arch/arm/boot/dts/qcom/msm8996-sde.dtsi

+78 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ 
		reg-names = "mdp_phys",

			"vbif_phys",

			"vbif_nrt_phys";



		/* clock and supply entries */

		clocks = <&clock_mmss clk_mdss_ahb_clk>,

			 <&clock_mmss clk_mdss_axi_clk>,

			 <&clock_mmss clk_mdp_clk_src>,
@@ -42,12 +44,63 @@ 
		clock-rate = <0 0 300000000 300000000 0 0 0 0>;

		clock-max-rate = <0 0 412500000 412500000 0 0 0 0>;



		/* interrupt config */

		interrupt-parent = <&intc>;

		interrupts = <0 83 0>;

		interrupt-controller;

		#interrupt-cells = <1>;

		iommus = <&mdp_smmu 0>;



		/* hw blocks */

		qcom,sde-off = <0x1000>;

		qcom,sde-ctl-off = <0x2000 0x2200 0x2400

				     0x2600 0x2800>;

		qcom,sde-mixer-off = <0x45000 0x46000 0x47000

				      0x48000 0x49000 0x4a000>;

		qcom,sde-dspp-off = <0x55000 0x57000>;

		qcom,sde-wb-off = <0x65000 0x65800 0x66000>;

		qcom,sde-wb-xin-id = <3 11 6>;

		qcom,sde-intf-off = <0x6b000 0x6b800

					0x6c000 0x6c800>;

		qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi";

		qcom,sde-pp-off = <0x71000 0x71800

					  0x72000 0x72800>;

		qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>;

		qcom,sde-cdm-off = <0x7a200>;

		qcom,sde-dsc-off = <0x10000 0x10000 0x0 0x0>;

		qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;



		qcom,sde-sspp-type = "vig", "vig", "vig",

				      "vig", "rgb", "rgb",

				      "rgb", "rgb", "dma",

				      "dma", "cursor", "cursor";



		qcom,sde-sspp-off = <0x5000 0x7000 0x9000

				      0xb000 0x15000 0x17000

				      0x19000 0x1b000 0x25000

				      0x27000 0x35000 0x37000>;



		qcom,sde-sspp-xin-id = <0 4 8

					12 1 5

					9 13 2

					10 7 7>;



		/* offsets are relative to "mdp_phys + qcom,sde-off */

		qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,

				  <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,

				  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,

				  <0x3b0 16>;

		qcom,sde-sspp-csc-off = <0x320>;

		qcom,sde-qseed-type = "qseedv2";

		qcom,sde-sspp-qseed-off = <0x200>;

		qcom,sde-mixer-linewidth = <2560>;

		qcom,sde-sspp-linewidth = <2560>;

		qcom,sde-mixer-blendstages = <0x7>;

		qcom,sde-highest-bank-bit = <0x2>;

		qcom,sde-panic-per-pipe;

		qcom,sde-has-cdp;

		qcom,sde-has-src-split;



		mmagic-supply = <&gdsc_mmagic_mdss>;

		vdd-supply = <&gdsc_mdss>;
@@ -93,6 +146,31 @@ 
			compatible = "qcom,smmu_rot_sec";

			iommus = <&rot_smmu 1>;

		};



		/* data and reg bus scale settings */

		mdss-data-bus {

			qcom,msm-bus,name = "mdss_sde";

			qcom,msm-bus,num-cases = <3>;

			qcom,msm-bus,num-paths = <3>;

			qcom,msm-bus,vectors-KBps =

				<22 512 0 0>, <23 512 0 0>, <25 512 0 0>,

				<22 512 0 6400000>, <23 512 0 6400000>,

					<25 512 0 6400000>,

				<22 512 0 6400000>, <23 512 0 6400000>,

					<25 512 0 6400000>;

		};



		mdss-reg-bus {

			qcom,msm-bus,name = "mdss_reg";

			qcom,msm-bus,num-cases = <4>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,active-only;

			qcom,msm-bus,vectors-KBps =

				<1 590 0 0>,

				<1 590 0 76800>,

				<1 590 0 160000>,

				<1 590 0 320000>;

		};

	};



	mdss_dsi0: qcom,mdss_dsi_ctrl0@994000 {

drivers/gpu/drm/msm/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -108,7 +108,6 @@ msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \ 
obj-$(CONFIG_DRM_MSM)	+= msm.o



obj-$(CONFIG_DRM_MSM) += sde/sde_hw_catalog.o \

	sde/sde_hw_catalog_8996.o \

	sde/sde_hw_cdm.o \

	sde/sde_hw_dspp.o \

	sde/sde_hw_intf.o \

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+1165 −15

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+34 −5
Original line number Diff line number Diff line
@@ -17,9 +17,14 @@ 
#include <linux/bug.h>

#include <linux/bitmap.h>

#include <linux/err.h>

#include <drm/drmP.h>



#define MAX_BLOCKS    8

#define MAX_LAYERS    12

/**

 * Max hardware block count: For ex: max 12 SSPP pipes or

 * 5 ctl paths. In all cases, it can have max 12 hardware blocks

 * based on current design

 */

#define MAX_BLOCKS    12



#define SDE_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28)    |\

		((MINOR & 0xFFF) << 16)  |\
@@ -225,11 +230,13 @@ enum { 
 * MACRO SDE_HW_BLK_INFO - information of HW blocks inside SDE

 * @id:                enum identifying this block

 * @base:              register base offset to mdss

 * @len:               length of hardware block

 * @features           bit mask identifying sub-blocks/features

 */

#define SDE_HW_BLK_INFO \

	u32 id; \

	u32 base; \

	u32 len; \

	unsigned long features; \



/**
@@ -588,10 +595,25 @@ struct sde_vbif_cfg { 
 * This is the main catalog data structure representing

 * this HW version. Contains number of instances,

 * register offsets, capabilities of the all MDSS HW sub-blocks.

 *

 * @max_sspp_linewidth max source pipe line width support.

 * @max_mixer_width    max layer mixer line width support.

 * @max_mixer_blendstages max layer mixer blend stages or

 *                       supported z order

 * @max_wb_linewidth   max writeback line width support.

 * @highest_bank_bit   highest memory bit setting for tile buffers.

 * @qseed_type         qseed2 or qseed3 support.

 */

struct sde_mdss_cfg {

	u32 hwversion;



	u32 max_sspp_linewidth;

	u32 max_mixer_width;

	u32 max_mixer_blendstages;

	u32 max_wb_linewidth;

	u32 highest_bank_bit;

	u32 qseed_type;



	u32 mdss_count;

	struct sde_mdss_base_cfg mdss[MAX_BLOCKS];
@@ -602,7 +624,7 @@ struct sde_mdss_cfg { 
	struct sde_ctl_cfg ctl[MAX_BLOCKS];



	u32 sspp_count;

	struct sde_sspp_cfg sspp[MAX_LAYERS];

	struct sde_sspp_cfg sspp[MAX_BLOCKS];



	u32 mixer_count;

	struct sde_lm_cfg mixer[MAX_BLOCKS];
@@ -650,7 +672,14 @@ struct sde_mdss_hw_cfg_handler { 
#define BLK_WB(s) ((s)->wb)

#define BLK_AD(s) ((s)->ad)



struct sde_mdss_cfg *sde_mdss_cfg_170_init(u32 step);

struct sde_mdss_cfg *sde_hw_catalog_init(u32 major, u32 minor, u32 step);

/**

 * sde_hw_catalog_init() - sde hardware catalog init API parses dtsi property

 * and stores all parsed offset, hardware capabilities in config structure.

 * @dev:          drm device node.

 * @hw_rev:       caller needs provide the hardware revision before parsing.

 *

 * Return: parsed sde config structure

 */

struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev);



#endif /* _SDE_HW_CATALOG_H */