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Commit b8262a6d authored by Anjali Singhai Jain's avatar Anjali Singhai Jain Committed by Jeff Kirsher
Browse files

i40e/i40evf: add VIRTCHNL_VF_OFFLOAD flag 



Add virtual channel offload capability to support RX polling mode in the
VF.

Change-ID: Ib643ae2a7506dfc75fc489fc207493fabefa4832
Signed-off-by: default avatarJingjing Wu <jingjing.wu@intel.com>
Signed-off-by: default avatarAnjali Singhai Jain <anjali.singhai@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 2b20c883

drivers/net/ethernet/intel/i40e/i40e_register.h

+7 −0
Original line number Original line Diff line number Diff line
@@ -873,6 +873,13 @@ 
#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)

#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)

#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31

#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31

#define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT)

#define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT)

#define I40E_GLINT_CTL 0x0003F800 /* Reset: CORER */

#define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT 0

#define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT)

#define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT 1

#define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT)

#define I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT 2

#define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT)

#define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */

#define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */

#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0

#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0

#define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT)

#define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT)

drivers/net/ethernet/intel/i40e/i40e_virtchnl.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -152,6 +152,7 @@ struct i40e_virtchnl_vsi_resource { 
#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ		0x00000008

#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ		0x00000008

#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG	0x00000010

#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG	0x00000010

#define I40E_VIRTCHNL_VF_OFFLOAD_VLAN		0x00010000

#define I40E_VIRTCHNL_VF_OFFLOAD_VLAN		0x00010000

#define I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING	0x00020000





struct i40e_virtchnl_vf_resource {

struct i40e_virtchnl_vf_resource {

	u16 num_vsis;

	u16 num_vsis;

drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c

+12 −0
Original line number Original line Diff line number Diff line
@@ -335,6 +335,18 @@ static void i40e_config_irq_link_list(struct i40e_vf *vf, u16 vsi_id, 
		wr32(hw, reg_idx, reg);

		wr32(hw, reg_idx, reg);

	}

	}





	/* if the vf is running in polling mode and using interrupt zero,

	 * need to disable auto-mask on enabling zero interrupt for VFs.

	 */

	if ((vf->driver_caps & I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING) &&

	    (vector_id == 0)) {

		reg = rd32(hw, I40E_GLINT_CTL);

		if (!(reg & I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK)) {

			reg |= I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;

			wr32(hw, I40E_GLINT_CTL, reg);

		}

	}



irq_list_done:

irq_list_done:

	i40e_flush(hw);

	i40e_flush(hw);

}

}

drivers/net/ethernet/intel/i40evf/i40e_virtchnl.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -152,6 +152,7 @@ struct i40e_virtchnl_vsi_resource { 
#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ		0x00000008

#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ		0x00000008

#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG	0x00000010

#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG	0x00000010

#define I40E_VIRTCHNL_VF_OFFLOAD_VLAN		0x00010000

#define I40E_VIRTCHNL_VF_OFFLOAD_VLAN		0x00010000

#define I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING	0x00020000





struct i40e_virtchnl_vf_resource {

struct i40e_virtchnl_vf_resource {

	u16 num_vsis;

	u16 num_vsis;