Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b4457411 authored by Taniya Das's avatar Taniya Das
Browse files

ARM: dts: msm: Add support for GDSCs for MSMFalcon/MSMtriton 



Support for the GDSCs which are required to be enabled/disabled by clients
on msmfalcon and msmtriton.

Change-Id: I0bad9d7bbee060ef70f3e8e6274fccc86fe9df6e
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 773f15cd

arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi

0 → 100644
+159 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	/* GCC GDSCs */

	gdsc_usb30: qcom,gdsc@10f004 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_usb30";

		reg = <0x10f004 0x4>;

		status = "disabled";

	};



	gdsc_ufs: qcom,gdsc@175004 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_ufs";

		reg = <0x175004 0x4>;

		status = "disabled";

	};



	gdsc_hlos1_vote_lpass_adsp: qcom,gdsc@17d034 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_hlos1_vote_lpass_adsp";

		reg = <0x17d034 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	gdsc_hlos1_vote_turing_adsp: qcom,gdsc@17d04c {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_hlos1_vote_turing_adsp";

		reg = <0x17d04c 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	gdsc_hlos2_vote_turing_adsp: qcom,gdsc@17e04c {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_hlos2_vote_turing_adsp";

		reg = <0x17e04c 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	/* MMSS GDSCs */

	bimc_smmu_hw_ctrl: syscon@c8ce024 {

	      compatible = "syscon";

	      reg = <0xc8ce024 0x4>;

	};



	gdsc_bimc_smmu: qcom,gdsc@c8ce020 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_bimc_smmu";

		reg = <0xc8ce020 0x4>;

		hw-ctrl-addr = <&bimc_smmu_hw_ctrl>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	gdsc_venus: qcom,gdsc@c8c1024 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_venus";

		reg = <0xc8c1024 0x4>;

		status = "disabled";

	};



	gdsc_venus_core0: qcom,gdsc@c8c1040 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_venus_core0";

		reg = <0xc8c1040 0x4>;

		status = "disabled";

	};



	gdsc_camss_top: qcom,gdsc@c8c34a0 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_camss_top";

		reg = <0xc8c34a0 0x4>;

		status = "disabled";

	};



	gdsc_vfe0: qcom,gdsc@c8c3664 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_vfe0";

		reg = <0xc8c3664 0x4>;

		status = "disabled";

	};



	gdsc_vfe1: qcom,gdsc@c8c3674 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_vfe1";

		reg = <0xc8c3674 0x4>;

		status = "disabled";

	};



	gdsc_cpp: qcom,gdsc@c8c36d4 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_cpp";

		reg = <0xc8c36d4 0x4>;

		status = "disabled";

	};



	gdsc_mdss: qcom,gdsc@c8c2304 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_mdss";

		reg = <0xc8c2304 0x4>;

		status = "disabled";

	};



	/* GPU GDSCs */

	gpu_cx_hw_ctrl: syscon@5066008 {

		compatible = "syscon";

		reg = <0x5066008 0x4>;

	};



	gdsc_gpu_cx: qcom,gdsc@5066004 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_gpu_cx";

		reg = <0x5066004 0x4>;

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <2000>;

		status = "disabled";

	};



	/* GPU GX GDSCs */

	gpu_gx_domain_addr: syscon@5065130 {

		compatible = "syscon";

		reg = <0x5065130 0x4>;

	};



	gpu_gx_sw_reset: syscon@5066090 {

		compatible = "syscon";

		reg = <0x5066090 0x4>;

	};



	gdsc_gpu_gx: qcom,gdsc@5066094 {

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_gpu_gx";

		reg = <0x5066094 0x4>;

		domain-addr = <&gpu_gx_domain_addr>;

		sw-reset = <&gpu_gx_sw_reset>;

		qcom,retain-periph;

		qcom,reset-aon-logic;

		status = "disabled";

	};

};

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+10 −1
Original line number Diff line number Diff line
@@ -675,7 +675,7 @@ 
#include "msmfalcon-ion.dtsi"

#include "msmfalcon-bus.dtsi"

#include "msmfalcon-regulator.dtsi"

#include "msm-gdsc-cobalt.dtsi"

#include "msm-gdsc-falcon.dtsi"



&gdsc_usb30 {

	clock-names = "core_clk";
@@ -699,6 +699,14 @@ 
	status = "ok";

};



&gdsc_hlos1_vote_turing_adsp {

	status = "ok";

};



&gdsc_hlos2_vote_turing_adsp {

	status = "ok";

};



&gdsc_venus {

	status = "ok";

};
@@ -749,5 +757,6 @@ 
&gdsc_gpu_cx {

	status = "ok";

};



#include "msm-pmfalcon.dtsi"

#include "msm-pm2falcon.dtsi"

arch/arm/boot/dts/qcom/msmtriton.dtsi

+76 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>



/ {

	model = "Qualcomm Technologies, Inc. MSMTRITON";
@@ -543,3 +544,78 @@ 
};



#include "msmtriton-ion.dtsi"

#include "msmfalcon-regulator.dtsi"

#include "msm-gdsc-falcon.dtsi"



&gdsc_usb30 {

	clock-names = "core_clk";

	clocks = <&clock_gcc GCC_USB30_MASTER_CLK>;

	status = "ok";

};



&gdsc_ufs {

	status = "ok";

};



&gdsc_bimc_smmu {

	clock-names = "bus_clk";

	clocks = <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;

	proxy-supply = <&gdsc_bimc_smmu>;

	qcom,proxy-consumer-enable;

	status = "ok";

};



&gdsc_hlos1_vote_lpass_adsp {

	status = "ok";

};



&gdsc_venus {

	status = "ok";

};



&gdsc_venus_core0 {

	qcom,support-hw-trigger;

	status = "ok";

};



&gdsc_camss_top {

	status = "ok";

};



&gdsc_vfe0 {

	parent-supply = <&gdsc_camss_top>;

	status = "ok";

};



&gdsc_vfe1 {

	parent-supply = <&gdsc_camss_top>;

	status = "ok";

};



&gdsc_cpp {

	parent-supply = <&gdsc_camss_top>;

	status = "ok";

};



&gdsc_mdss {

	clock-names = "bus_clk", "rot_clk";

	clocks = <&clock_mmss MMSS_MDSS_AXI_CLK>,

		 <&clock_mmss MMSS_MDSS_ROT_CLK>;

	proxy-supply = <&gdsc_mdss>;

	qcom,proxy-consumer-enable;

	status = "ok";

};



&gdsc_gpu_gx {

	clock-names = "bimc_core_clk", "core_clk", "core_root_clk";

	clocks = <&clock_gcc GCC_GPU_BIMC_GFX_CLK>,

		 <&clock_gfx GPUCC_GFX3D_CLK>,

		 <&clock_gfx GFX3D_CLK_SRC>;

	qcom,force-enable-root-clk;

	parent-supply = <&gfx_vreg_corner>;

	status = "ok";

};



&gdsc_gpu_cx {

	status = "ok";

};