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Commit b355d4f7 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.4.171 into android-4.4 



Changes in 4.4.171
	ALSA: hda/realtek - Disable headset Mic VREF for headset mode of ALC225
	btrfs: cleanup, stop casting for extent_map->lookup everywhere
	btrfs: Enhance chunk validation check
	Btrfs: add validadtion checks for chunk loading
	Btrfs: check inconsistence between chunk and block group
	Btrfs: fix em leak in find_first_block_group
	Btrfs: detect corruption when non-root leaf has zero item
	Btrfs: check btree node's nritems
	Btrfs: fix BUG_ON in btrfs_mark_buffer_dirty
	Btrfs: memset to avoid stale content in btree node block
	Btrfs: improve check_node to avoid reading corrupted nodes
	Btrfs: kill BUG_ON in run_delayed_tree_ref
	Btrfs: memset to avoid stale content in btree leaf
	Btrfs: fix emptiness check for dirtied extent buffers at check_leaf()
	btrfs: struct-funcs, constify readers
	btrfs: Refactor check_leaf function for later expansion
	btrfs: Check if item pointer overlaps with the item itself
	btrfs: Add sanity check for EXTENT_DATA when reading out leaf
	btrfs: Add checker for EXTENT_CSUM
	btrfs: Move leaf and node validation checker to tree-checker.c
	btrfs: tree-checker: Enhance btrfs_check_node output
	btrfs: tree-checker: Fix false panic for sanity test
	btrfs: tree-checker: Add checker for dir item
	btrfs: tree-checker: use %zu format string for size_t
	btrfs: tree-check: reduce stack consumption in check_dir_item
	btrfs: tree-checker: Verify block_group_item
	btrfs: tree-checker: Detect invalid and empty essential trees
	btrfs: validate type when reading a chunk
	btrfs: Check that each block group has corresponding chunk at mount time
	btrfs: Verify that every chunk has corresponding block group at mount time
	btrfs: tree-checker: Check level for leaves and nodes
	btrfs: tree-checker: Fix misleading group system information
	CIFS: Do not hide EINTR after sending network packets
	cifs: Fix potential OOB access of lock element array
	usb: cdc-acm: send ZLP for Telit 3G Intel based modems
	USB: storage: don't insert sane sense for SPC3+ when bad sense specified
	USB: storage: add quirk for SMI SM3350
	USB: Add USB_QUIRK_DELAY_CTRL_MSG quirk for Corsair K70 RGB
	slab: alien caches must not be initialized if the allocation of the alien cache failed
	PCI: altera: Fix altera_pcie_link_is_up()
	PCI: altera: Reorder read/write functions
	PCI: altera: Check link status before retrain link
	PCI: altera: Poll for link up status after retraining the link
	PCI: altera: Poll for link training status after retraining the link
	PCI: altera: Rework config accessors for use without a struct pci_bus
	PCI: altera: Move retrain from fixup to altera_pcie_host_init()
	ACPI: power: Skip duplicate power resource references in _PRx
	i2c: dev: prevent adapter retries and timeout being set as minus value
	crypto: cts - fix crash on short inputs
	ext4: fix a potential fiemap/page fault deadlock w/ inline_data
	sunrpc: use-after-free in svc_process_common()
	Linux 4.4.171

Change-Id: If59c94897d4f135b24d45772a7db116503695ba7
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents e137948e c5feba43

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 4

PATCHLEVEL = 4

SUBLEVEL = 170

SUBLEVEL = 171

EXTRAVERSION =

NAME = Blurry Fish Butt

crypto/cts.c

+4 −4
Original line number Diff line number Diff line
@@ -137,8 +137,8 @@ static int crypto_cts_encrypt(struct blkcipher_desc *desc, 
	lcldesc.info = desc->info;

	lcldesc.flags = desc->flags;



	if (tot_blocks == 1) {

		err = crypto_blkcipher_encrypt_iv(&lcldesc, dst, src, bsize);

	if (tot_blocks <= 1) {

		err = crypto_blkcipher_encrypt_iv(&lcldesc, dst, src, nbytes);

	} else if (nbytes <= bsize * 2) {

		err = cts_cbc_encrypt(ctx, desc, dst, src, 0, nbytes);

	} else {
@@ -232,8 +232,8 @@ static int crypto_cts_decrypt(struct blkcipher_desc *desc, 
	lcldesc.info = desc->info;

	lcldesc.flags = desc->flags;



	if (tot_blocks == 1) {

		err = crypto_blkcipher_decrypt_iv(&lcldesc, dst, src, bsize);

	if (tot_blocks <= 1) {

		err = crypto_blkcipher_decrypt_iv(&lcldesc, dst, src, nbytes);

	} else if (nbytes <= bsize * 2) {

		err = cts_cbc_decrypt(ctx, desc, dst, src, 0, nbytes);

	} else {

drivers/acpi/power.c

+22 −0
Original line number Diff line number Diff line
@@ -131,6 +131,23 @@ void acpi_power_resources_list_free(struct list_head *list) 
	}

}



static bool acpi_power_resource_is_dup(union acpi_object *package,

				       unsigned int start, unsigned int i)

{

	acpi_handle rhandle, dup;

	unsigned int j;



	/* The caller is expected to check the package element types */

	rhandle = package->package.elements[i].reference.handle;

	for (j = start; j < i; j++) {

		dup = package->package.elements[j].reference.handle;

		if (dup == rhandle)

			return true;

	}



	return false;

}



int acpi_extract_power_resources(union acpi_object *package, unsigned int start,

				 struct list_head *list)

{
@@ -150,6 +167,11 @@ int acpi_extract_power_resources(union acpi_object *package, unsigned int start, 
			err = -ENODEV;

			break;

		}



		/* Some ACPI tables contain duplicate power resource references */

		if (acpi_power_resource_is_dup(package, start, i))

			continue;



		err = acpi_add_power_resource(rhandle);

		if (err)

			break;

drivers/i2c/i2c-dev.c

+6 −0
Original line number Diff line number Diff line
@@ -459,9 +459,15 @@ static long i2cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 
		return i2cdev_ioctl_smbus(client, arg);



	case I2C_RETRIES:

		if (arg > INT_MAX)

			return -EINVAL;



		client->adapter->retries = arg;

		break;

	case I2C_TIMEOUT:

		if (arg > INT_MAX)

			return -EINVAL;



		/* For historical reasons, user-space sets the timeout

		 * value in units of 10 ms.

		 */

drivers/pci/host/pcie-altera.c

+147 −54
Original line number Diff line number Diff line
@@ -40,8 +40,10 @@ 
#define P2A_INT_ENABLE			0x3070

#define P2A_INT_ENA_ALL			0xf

#define RP_LTSSM			0x3c64

#define RP_LTSSM_MASK			0x1f

#define LTSSM_L0			0xf



#define PCIE_CAP_OFFSET			0x80

/* TLP configuration type 0 and 1 */

#define TLP_FMTTYPE_CFGRD0		0x04	/* Configuration Read Type 0 */

#define TLP_FMTTYPE_CFGWR0		0x44	/* Configuration Write Type 0 */
@@ -60,6 +62,9 @@ 
#define TLP_LOOP			500

#define RP_DEVFN			0



#define LINK_UP_TIMEOUT			HZ

#define LINK_RETRAIN_TIMEOUT		HZ



#define INTX_NUM			4



#define DWORD_MASK			3
@@ -80,25 +85,21 @@ struct tlp_rp_regpair_t { 
	u32 reg1;

};



static void altera_pcie_retrain(struct pci_dev *dev)

static inline void cra_writel(struct altera_pcie *pcie, const u32 value,

			      const u32 reg)

{

	u16 linkcap, linkstat;



	/*

	 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but

	 * current speed is 2.5 GB/s.

	 */

	pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);

	writel_relaxed(value, pcie->cra_base + reg);

}



	if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)

		return;

static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)

{

	return readl_relaxed(pcie->cra_base + reg);

}



	pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);

	if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB)

		pcie_capability_set_word(dev, PCI_EXP_LNKCTL,

					 PCI_EXP_LNKCTL_RL);

static bool altera_pcie_link_is_up(struct altera_pcie *pcie)

{

	return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);

}

DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);



/*

 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
@@ -119,17 +120,6 @@ static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, 
	return false;

}



static inline void cra_writel(struct altera_pcie *pcie, const u32 value,

			      const u32 reg)

{

	writel_relaxed(value, pcie->cra_base + reg);

}



static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)

{

	return readl_relaxed(pcie->cra_base + reg);

}



static void tlp_write_tx(struct altera_pcie *pcie,

			 struct tlp_rp_regpair_t *tlp_rp_regdata)

{
@@ -138,11 +128,6 @@ static void tlp_write_tx(struct altera_pcie *pcie, 
	cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);

}



static bool altera_pcie_link_is_up(struct altera_pcie *pcie)

{

	return !!(cra_readl(pcie, RP_LTSSM) & LTSSM_L0);

}



static bool altera_pcie_valid_config(struct altera_pcie *pcie,

				     struct pci_bus *bus, int dev)

{
@@ -286,22 +271,14 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn, 
	return PCIBIOS_SUCCESSFUL;

}



static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,

				int where, int size, u32 *value)

static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,

				 unsigned int devfn, int where, int size,

				 u32 *value)

{

	struct altera_pcie *pcie = bus->sysdata;

	int ret;

	u32 data;

	u8 byte_en;



	if (altera_pcie_hide_rc_bar(bus, devfn, where))

		return PCIBIOS_BAD_REGISTER_NUMBER;



	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {

		*value = 0xffffffff;

		return PCIBIOS_DEVICE_NOT_FOUND;

	}



	switch (size) {

	case 1:

		byte_en = 1 << (where & 3);
@@ -314,7 +291,7 @@ static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn, 
		break;

	}



	ret = tlp_cfg_dword_read(pcie, bus->number, devfn,

	ret = tlp_cfg_dword_read(pcie, busno, devfn,

				 (where & ~DWORD_MASK), byte_en, &data);

	if (ret != PCIBIOS_SUCCESSFUL)

		return ret;
@@ -334,20 +311,14 @@ static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn, 
	return PCIBIOS_SUCCESSFUL;

}



static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,

				 int where, int size, u32 value)

static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,

				  unsigned int devfn, int where, int size,

				  u32 value)

{

	struct altera_pcie *pcie = bus->sysdata;

	u32 data32;

	u32 shift = 8 * (where & 3);

	u8 byte_en;



	if (altera_pcie_hide_rc_bar(bus, devfn, where))

		return PCIBIOS_BAD_REGISTER_NUMBER;



	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))

		return PCIBIOS_DEVICE_NOT_FOUND;



	switch (size) {

	case 1:

		data32 = (value & 0xff) << shift;
@@ -363,8 +334,40 @@ static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn, 
		break;

	}



	return tlp_cfg_dword_write(pcie, bus->number, devfn,

		(where & ~DWORD_MASK), byte_en, data32);

	return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),

				   byte_en, data32);

}



static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,

				int where, int size, u32 *value)

{

	struct altera_pcie *pcie = bus->sysdata;



	if (altera_pcie_hide_rc_bar(bus, devfn, where))

		return PCIBIOS_BAD_REGISTER_NUMBER;



	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {

		*value = 0xffffffff;

		return PCIBIOS_DEVICE_NOT_FOUND;

	}



	return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,

				     value);

}



static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,

				 int where, int size, u32 value)

{

	struct altera_pcie *pcie = bus->sysdata;



	if (altera_pcie_hide_rc_bar(bus, devfn, where))

		return PCIBIOS_BAD_REGISTER_NUMBER;



	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))

		return PCIBIOS_DEVICE_NOT_FOUND;



	return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,

				     value);

}



static struct pci_ops altera_pcie_ops = {
@@ -372,6 +375,90 @@ static struct pci_ops altera_pcie_ops = { 
	.write = altera_pcie_cfg_write,

};



static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,

				unsigned int devfn, int offset, u16 *value)

{

	u32 data;

	int ret;



	ret = _altera_pcie_cfg_read(pcie, busno, devfn,

				    PCIE_CAP_OFFSET + offset, sizeof(*value),

				    &data);

	*value = data;

	return ret;

}



static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,

				 unsigned int devfn, int offset, u16 value)

{

	return _altera_pcie_cfg_write(pcie, busno, devfn,

				      PCIE_CAP_OFFSET + offset, sizeof(value),

				      value);

}



static void altera_wait_link_retrain(struct altera_pcie *pcie)

{

	u16 reg16;

	unsigned long start_jiffies;



	/* Wait for link training end. */

	start_jiffies = jiffies;

	for (;;) {

		altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,

				     PCI_EXP_LNKSTA, &reg16);

		if (!(reg16 & PCI_EXP_LNKSTA_LT))

			break;



		if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {

			dev_err(&pcie->pdev->dev, "link retrain timeout\n");

			break;

		}

		udelay(100);

	}



	/* Wait for link is up */

	start_jiffies = jiffies;

	for (;;) {

		if (altera_pcie_link_is_up(pcie))

			break;



		if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {

			dev_err(&pcie->pdev->dev, "link up timeout\n");

			break;

		}

		udelay(100);

	}

}



static void altera_pcie_retrain(struct altera_pcie *pcie)

{

	u16 linkcap, linkstat, linkctl;



	if (!altera_pcie_link_is_up(pcie))

		return;



	/*

	 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but

	 * current speed is 2.5 GB/s.

	 */

	altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,

			     &linkcap);

	if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)

		return;



	altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,

			     &linkstat);

	if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {

		altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,

				     PCI_EXP_LNKCTL, &linkctl);

		linkctl |= PCI_EXP_LNKCTL_RL;

		altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,

				      PCI_EXP_LNKCTL, linkctl);



		altera_wait_link_retrain(pcie);

	}

}



static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,

				irq_hw_number_t hwirq)

{
@@ -506,6 +593,11 @@ static int altera_pcie_parse_dt(struct altera_pcie *pcie) 
	return 0;

}



static void altera_pcie_host_init(struct altera_pcie *pcie)

{

	altera_pcie_retrain(pcie);

}



static int altera_pcie_probe(struct platform_device *pdev)

{

	struct altera_pcie *pcie;
@@ -543,6 +635,7 @@ static int altera_pcie_probe(struct platform_device *pdev) 
	cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);

	/* enable all interrupts */

	cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);

	altera_pcie_host_init(pcie);



	bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,

				pcie, &pcie->resources);