Merge "clk: msm: mdss: change DP clock rate in order of KHz" (b2b4bbae) · Commits · e / devices / android_kernel_sony_msm8998

drivers/clk/msm/clock-mmss-cobalt.c

+12 −12

Original line number	Diff line number	Diff line
		@@ -1113,16 +1113,16 @@ static struct rcg_clk dp_pixel_clk_src = {
		.parent = &ext_dp_phy_pll_vco.c,
		.ops = &clk_ops_rcg_dp,
		.flags = CLKFLAG_NO_RATE_CACHE,
		VDD_DIG_FMAX_MAP3(LOWER, 148380000, LOW, 296740000,
		NOMINAL, 593470000),
		VDD_DIG_FMAX_MAP3(LOWER, 148380, LOW, 296740,
		NOMINAL, 593470),
		CLK_INIT(dp_pixel_clk_src.c),
		},
		};

		static struct clk_freq_tbl ftbl_dp_link_clk_src[] = {
		F_SLEW( 162000000, 324000000, ext_dp_phy_pll_link, 2, 0, 0),
		F_SLEW( 270000000, 540000000, ext_dp_phy_pll_link, 2, 0, 0),
		F_SLEW( 540000000, 1080000000, ext_dp_phy_pll_link, 2, 0, 0),
		F_SLEW( 162000, 324000, ext_dp_phy_pll_link, 2, 0, 0),
		F_SLEW( 270000, 540000, ext_dp_phy_pll_link, 2, 0, 0),
		F_SLEW( 540000, 1080000, ext_dp_phy_pll_link, 2, 0, 0),
		F_END
		};

		@@ -1136,8 +1136,8 @@ static struct rcg_clk dp_link_clk_src = {
		.dbg_name = "dp_link_clk_src",
		.ops = &clk_ops_rcg,
		.flags = CLKFLAG_NO_RATE_CACHE,
		VDD_DIG_FMAX_MAP3(LOWER, 162000000, LOW, 270000000,
		NOMINAL, 540000000),
		VDD_DIG_FMAX_MAP3(LOWER, 162000, LOW, 270000,
		NOMINAL, 540000),
		CLK_INIT(dp_link_clk_src.c),
		},
		};
		@@ -1149,9 +1149,9 @@ static struct rcg_clk dp_link_clk_src = {
		* clocks.
		*/
		static struct clk_freq_tbl ftbl_dp_crypto_clk_src[] = {
		F_MM( 101250000, ext_dp_phy_pll_link, 1, 5, 16),
		F_MM( 168750000, ext_dp_phy_pll_link, 1, 5, 16),
		F_MM( 337500000, ext_dp_phy_pll_link, 1, 5, 16),
		F_MM( 101250, ext_dp_phy_pll_link, 1, 5, 16),
		F_MM( 168750, ext_dp_phy_pll_link, 1, 5, 16),
		F_MM( 337500, ext_dp_phy_pll_link, 1, 5, 16),
		F_END
		};

		@@ -1164,8 +1164,8 @@ static struct rcg_clk dp_crypto_clk_src = {
		.c = {
		.dbg_name = "dp_crypto_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(LOWER, 101250000, LOW, 168750000,
		NOMINAL, 337500000),
		VDD_DIG_FMAX_MAP3(LOWER, 101250, LOW, 168750,
		NOMINAL, 337500),
		CLK_INIT(dp_crypto_clk_src.c),
		},
		};

drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c

+17 −17

Original line number	Diff line number	Diff line
		@@ -190,9 +190,9 @@ int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate)
		QSERDES_COM_CLK_SEL, 0x30);

		/* Different for each clock rates */
		if (rate == DP_VCO_HSCLK_RATE_1620MHz) {
		pr_debug("%s: VCO rate: %lld\n", __func__,
		DP_VCO_RATE_8100MHz);
		if (rate == DP_VCO_HSCLK_RATE_1620MHZDIV1000) {
		pr_debug("%s: VCO rate: %ld\n", __func__,
		DP_VCO_RATE_8100MHZDIV1000);
		MDSS_PLL_REG_W(dp_res->pll_base,
		QSERDES_COM_SYS_CLK_CTRL, 0x02);
		MDSS_PLL_REG_W(dp_res->pll_base,
		@@ -215,9 +215,9 @@ int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate)
		QSERDES_COM_LOCK_CMP2_MODE0, 0x21);
		MDSS_PLL_REG_W(dp_res->pll_base,
		QSERDES_COM_LOCK_CMP3_MODE0, 0x00);
		} else if (rate == DP_VCO_HSCLK_RATE_2700MHz) {
		pr_debug("%s: VCO rate: %lld\n", __func__,
		DP_VCO_RATE_8100MHz);
		} else if (rate == DP_VCO_HSCLK_RATE_2700MHZDIV1000) {
		pr_debug("%s: VCO rate: %ld\n", __func__,
		DP_VCO_RATE_8100MHZDIV1000);
		MDSS_PLL_REG_W(dp_res->pll_base,
		QSERDES_COM_SYS_CLK_CTRL, 0x06);
		MDSS_PLL_REG_W(dp_res->pll_base,
		@@ -240,9 +240,9 @@ int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate)
		QSERDES_COM_LOCK_CMP2_MODE0, 0x38);
		MDSS_PLL_REG_W(dp_res->pll_base,
		QSERDES_COM_LOCK_CMP3_MODE0, 0x00);
		} else if (rate == DP_VCO_HSCLK_RATE_5400MHz) {
		pr_debug("%s: VCO rate: %lld\n", __func__,
		DP_VCO_RATE_10800MHz);
		} else if (rate == DP_VCO_HSCLK_RATE_5400MHZDIV1000) {
		pr_debug("%s: VCO rate: %ld\n", __func__,
		DP_VCO_RATE_10800MHZDIV1000);
		MDSS_PLL_REG_W(dp_res->pll_base,
		QSERDES_COM_SYS_CLK_CTRL, 0x06);
		MDSS_PLL_REG_W(dp_res->pll_base,
		@@ -272,8 +272,8 @@ int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate)
		/* Make sure the PLL register writes are done */
		wmb();

		if ((rate == DP_VCO_HSCLK_RATE_1620MHz)
		\|\| (rate == DP_VCO_HSCLK_RATE_2700MHz)) {
		if ((rate == DP_VCO_HSCLK_RATE_1620MHZDIV1000)
		\|\| (rate == DP_VCO_HSCLK_RATE_2700MHZDIV1000)) {
		MDSS_PLL_REG_W(dp_res->phy_base,
		DP_PHY_VCO_DIV, 0x1);
		} else {
		@@ -713,14 +713,14 @@ unsigned long dp_vco_get_rate(struct clk *c)
		pr_err("%s: unsupported div. Phy_mode: %d\n", __func__, div);

		if (link2xclk_div == 10) {
		vco_rate = DP_VCO_HSCLK_RATE_2700MHz;
		vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;
		} else {
		if (hsclk_div == 5)
		vco_rate = DP_VCO_HSCLK_RATE_1620MHz;
		vco_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000;
		else if (hsclk_div == 3)
		vco_rate = DP_VCO_HSCLK_RATE_2700MHz;
		vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;
		else
		vco_rate = DP_VCO_HSCLK_RATE_5400MHz;
		vco_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000;
		}

		pr_debug("returning vco rate = %lu\n", (unsigned long)vco_rate);
		@@ -737,8 +737,8 @@ long dp_vco_round_rate(struct clk *c, unsigned long rate)

		if (rate <= vco->min_rate)
		rrate = vco->min_rate;
		else if (rate <= DP_VCO_HSCLK_RATE_2700MHz)
		rrate = DP_VCO_HSCLK_RATE_2700MHz;
		else if (rate <= DP_VCO_HSCLK_RATE_2700MHZDIV1000)
		rrate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;
		else
		rrate = vco->max_rate;

drivers/clk/msm/mdss/mdss-dp-pll-cobalt.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -93,8 +93,8 @@ static struct clk_mux_ops mdss_mux_ops = {
		};

		static struct dp_pll_vco_clk dp_vco_clk = {
		.min_rate = DP_VCO_HSCLK_RATE_1620MHz,
		.max_rate = DP_VCO_HSCLK_RATE_5400MHz,
		.min_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000,
		.max_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000,
		.c = {
		.dbg_name = "dp_vco_clk",
		.ops = &dp_cobalt_vco_clk_ops,

drivers/clk/msm/mdss/mdss-dp-pll-cobalt.h

+5 −5

Original line number	Diff line number	Diff line
		@@ -155,12 +155,12 @@
		#define DP_PLL_POLL_SLEEP_US 500
		#define DP_PLL_POLL_TIMEOUT_US 10000

		#define DP_VCO_RATE_8100MHz 8100000000ULL
		#define DP_VCO_RATE_10800MHz 10800000000ULL
		#define DP_VCO_RATE_8100MHZDIV1000 8100000UL
		#define DP_VCO_RATE_10800MHZDIV1000 10800000UL

		#define DP_VCO_HSCLK_RATE_1620MHz 1620000000ULL
		#define DP_VCO_HSCLK_RATE_2700MHz 2700000000ULL
		#define DP_VCO_HSCLK_RATE_5400MHz 5400000000ULL
		#define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL
		#define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL
		#define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL

		int dp_vco_set_rate(struct clk *c, unsigned long rate);
		unsigned long dp_vco_get_rate(struct clk *c);

drivers/video/fbdev/msm/mdss_dp.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -1057,11 +1057,13 @@ int mdss_dp_on(struct mdss_panel_data *pdata)
		pr_debug("link_rate = 0x%x\n", dp_drv->link_rate);

		dp_drv->power_data[DP_CTRL_PM].clk_config[0].rate =
		dp_drv->link_rate * DP_LINK_RATE_MULTIPLIER;
		((dp_drv->link_rate * DP_LINK_RATE_MULTIPLIER) /
		1000); /* KHz */

		dp_drv->pixel_rate = dp_drv->panel_data.panel_info.clk_rate;
		dp_drv->power_data[DP_CTRL_PM].clk_config[3].rate =
		dp_drv->pixel_rate;
		(dp_drv->pixel_rate /
		1000); /* KHz */

		ret = mdss_dp_clk_ctrl(dp_drv, DP_CTRL_PM, true);
		if (ret) {