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Commit b0dd9c02 authored by Marc Zyngier's avatar Marc Zyngier Committed by Catalin Marinas
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arm64: Rework alternate sequence for ARM erratum 845719 



The workaround for erratum 845719 is currently using
a branch between two alternate sequences, which is
quite fragile, and that we are going to break as we
rework the alternative code.

This patch reworks the workaround to fit in a single
alternative sequence. The generated code itself is
unchanged.

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 10b48f7e

arch/arm64/kernel/entry.S

+15 −12
Original line number Diff line number Diff line
@@ -124,21 +124,24 @@ 
	msr	sp_el0, x23



#ifdef CONFIG_ARM64_ERRATUM_845719

	alternative_insn						\

	"nop",								\

	"tbz x22, #4, 1f",						\

	ARM64_WORKAROUND_845719



#undef SEQUENCE_ORG

#undef SEQUENCE_ALT



#ifdef CONFIG_PID_IN_CONTEXTIDR

	alternative_insn						\

	"nop; nop",							\

	"mrs x29, contextidr_el1; msr contextidr_el1, x29; 1:",		\

	ARM64_WORKAROUND_845719



#define SEQUENCE_ORG	"nop ; nop ; nop"

#define SEQUENCE_ALT	"tbz x22, #4, 1f ; mrs x29, contextidr_el1; msr contextidr_el1, x29; 1:"



#else

	alternative_insn						\

	"nop",								\

	"msr contextidr_el1, xzr; 1:",					\

	ARM64_WORKAROUND_845719



#define SEQUENCE_ORG	"nop ; nop"

#define SEQUENCE_ALT	"tbz x22, #4, 1f ; msr contextidr_el1, xzr; 1:"



#endif



	alternative_insn SEQUENCE_ORG, SEQUENCE_ALT, ARM64_WORKAROUND_845719



#endif

	.endif

	msr	elr_el1, x21			// set up the return data