Loading arch/arm/boot/dts/qcom/dsi-panel-rm67195-amoled-fhd-cmd.dtsi +6 −4 Original line number Diff line number Diff line Loading @@ -20,11 +20,11 @@ qcom,mdss-dsi-stream = <0>; qcom,mdss-dsi-panel-width = <1080>; qcom,mdss-dsi-panel-height = <1920>; qcom,mdss-dsi-h-front-porch = <32>; qcom,mdss-dsi-h-back-porch = <40>; qcom,mdss-dsi-h-pulse-width = <8>; qcom,mdss-dsi-h-front-porch = <120>; qcom,mdss-dsi-h-back-porch = <60>; qcom,mdss-dsi-h-pulse-width = <12>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <16>; qcom,mdss-dsi-v-back-porch = <12>; qcom,mdss-dsi-v-front-porch = <8>; qcom,mdss-dsi-v-pulse-width = <4>; qcom,mdss-dsi-h-left-border = <0>; Loading Loading @@ -104,6 +104,8 @@ qcom,mdss-dsi-lane-1-state; qcom,mdss-dsi-lane-2-state; qcom,mdss-dsi-lane-3-state; qcom,mdss-dsi-t-clk-post = <0x0d>; qcom,mdss-dsi-t-clk-pre = <0x2f>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,mdss-dsi-te-pin-select = <1>; Loading arch/arm/boot/dts/qcom/sdm630-mdss-panels.dtsi +6 −6 Original line number Diff line number Diff line Loading @@ -152,11 +152,11 @@ }; &dsi_rm67195_amoled_fhd_cmd { qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 19 07 08 05 03 04 a0]; qcom,mdss-dsi-panel-timings-phy-v2 = [24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1a 08 09 05 03 04 a0]; qcom,mdss-dsi-t-clk-post = <0x0d>; qcom,mdss-dsi-t-clk-pre = <0x2d>; qcom,mdss-dsi-t-clk-pre = <0x2f>; }; arch/arm/boot/dts/qcom/sdm660-mdss-panels.dtsi +6 −6 Original line number Diff line number Diff line Loading @@ -267,11 +267,11 @@ }; &dsi_rm67195_amoled_fhd_cmd { qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 19 07 08 05 03 04 a0]; qcom,mdss-dsi-panel-timings-phy-v2 = [24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1a 08 09 05 03 04 a0]; qcom,mdss-dsi-t-clk-post = <0x0d>; qcom,mdss-dsi-t-clk-pre = <0x2d>; qcom,mdss-dsi-t-clk-pre = <0x2f>; }; Loading
arch/arm/boot/dts/qcom/dsi-panel-rm67195-amoled-fhd-cmd.dtsi +6 −4 Original line number Diff line number Diff line Loading @@ -20,11 +20,11 @@ qcom,mdss-dsi-stream = <0>; qcom,mdss-dsi-panel-width = <1080>; qcom,mdss-dsi-panel-height = <1920>; qcom,mdss-dsi-h-front-porch = <32>; qcom,mdss-dsi-h-back-porch = <40>; qcom,mdss-dsi-h-pulse-width = <8>; qcom,mdss-dsi-h-front-porch = <120>; qcom,mdss-dsi-h-back-porch = <60>; qcom,mdss-dsi-h-pulse-width = <12>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <16>; qcom,mdss-dsi-v-back-porch = <12>; qcom,mdss-dsi-v-front-porch = <8>; qcom,mdss-dsi-v-pulse-width = <4>; qcom,mdss-dsi-h-left-border = <0>; Loading Loading @@ -104,6 +104,8 @@ qcom,mdss-dsi-lane-1-state; qcom,mdss-dsi-lane-2-state; qcom,mdss-dsi-lane-3-state; qcom,mdss-dsi-t-clk-post = <0x0d>; qcom,mdss-dsi-t-clk-pre = <0x2f>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,mdss-dsi-te-pin-select = <1>; Loading
arch/arm/boot/dts/qcom/sdm630-mdss-panels.dtsi +6 −6 Original line number Diff line number Diff line Loading @@ -152,11 +152,11 @@ }; &dsi_rm67195_amoled_fhd_cmd { qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 19 07 08 05 03 04 a0]; qcom,mdss-dsi-panel-timings-phy-v2 = [24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1a 08 09 05 03 04 a0]; qcom,mdss-dsi-t-clk-post = <0x0d>; qcom,mdss-dsi-t-clk-pre = <0x2d>; qcom,mdss-dsi-t-clk-pre = <0x2f>; };
arch/arm/boot/dts/qcom/sdm660-mdss-panels.dtsi +6 −6 Original line number Diff line number Diff line Loading @@ -267,11 +267,11 @@ }; &dsi_rm67195_amoled_fhd_cmd { qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 19 07 08 05 03 04 a0]; qcom,mdss-dsi-panel-timings-phy-v2 = [24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1f 08 09 05 03 04 a0 24 1a 08 09 05 03 04 a0]; qcom,mdss-dsi-t-clk-post = <0x0d>; qcom,mdss-dsi-t-clk-pre = <0x2d>; qcom,mdss-dsi-t-clk-pre = <0x2f>; };